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TheNetBurst microarchitecture,^[1][2] calledP68 insideIntel, was the successor to theP6 microarchitecture in thex86 family ofcentral processing units (CPUs) made by Intel. The first CPU to use this architecture was theWillamette-core Pentium 4, released on November 20, 2000, and the first of thePentium 4 CPUs; all subsequent Pentium 4 andPentium D variants have also been based on NetBurst. In mid-2001, Intel released theFoster core, which was also based on NetBurst, thus switching theXeon CPUs to the new architecture as well. Pentium 4-basedCeleron CPUs also use the NetBurst architecture. It was discontinued in 2010 and replaced with theCore microarchitecture based on P6, released in July 2006.

The NetBurst microarchitecture includes features such asHyper-threading,Hyper Pipelined Technology,Rapid Execution Engine,Execution Trace Cache, andreplay system which all were introduced for the first time in this particular microarchitecture, and some never appeared again afterwards.

Hyper-threading is Intel's proprietarysimultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 processors. Intel introduced it with NetBurst processors in 2002. Later Intel reintroduced it in theNehalem microarchitecture after its absence in the Core 2.

The Northwood and Willamette cores feature an external Front Side Bus (FSB) that runs at 100 MHz which transfers four bits per clock cycle, thus having an effective speed of 400 MHz. Later revisions of the Northwood core, along with the Prescott core (and derivatives) have an effective 800 MHz front-side bus (200 MHz quad pumped).[1]

The Willamette and Northwood cores contain a 20-stageinstruction pipeline. This is a significant increase in the number of stages compared to the Pentium III, which had only 10 stages in its pipeline. The Prescott core increased the length of the pipeline to 31 stages. A drawback of longer pipelines is the increase in the number of stages that need to be traced back in the event of a branch misprediction, increasing the penalty of said misprediction. To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reducesbranch mispredictions by 33% overPentium III.^[3] In reality, the longer pipeline resulted in reduced efficiency through a lower number ofinstructions per clock (IPC) executed as high enough clock speeds were not able to be reached to offset lost performance due to larger than expected increase in power consumption and heat.

With this technology, the twoarithmetic logic units (ALUs) in the core of the CPU are double-pumped, meaning that they actually operate at twice the core clock frequency. For example, in a 3.8 GHz processor, the ALUs will effectively be operating at 7.6 GHz. The reason behind this is to generally make up for the low IPC count; additionally this considerably enhances the integer performance of the CPU. Intel also replaced the high-speedbarrel shifter with a shift/rotate execution unit that operates at the same frequency as the CPU core. The downside is that certain instructions are now much slower (relatively and absolutely)^{[note 1]} than before, making optimization for multiple target CPUs difficult. An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the i386, including the main competitor processor,Athlon.

Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache. It stores decodedmicro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving considerable time. Moreover, the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution.^[4] Intel later introduced a similar but simpler concept withSandy Bridge calledmicro-operation cache (UOP cache).

The replay system is a subsystem within the Intel Pentium 4 processor to catch operations that have been mistakenly sent for execution by the processor's scheduler. Operations caught by the replay system are then re-executed in a loop until the conditions necessary for their proper execution have been fulfilled.

The Intel NetBurst architecture allowsbranch prediction hints to be inserted into the code to tell whether the static prediction should be taken or not taken, while this feature was abandoned in later Intel processors. According to Intel, NetBurst's branch prediction algorithm is 33% better than the one in P6.^[5][6]

Despite these enhancements, the NetBurst architecture created obstacles for engineers trying to scale up its performance. With this microarchitecture, Intel planned to attain clock speeds of 10 GHz,^[7] but because of rising clock speeds, Intel faced increasing problems with keeping power/heat dissipation within normal, usable function. Intel reached a speed barrier of 3.8 GHz in November 2004 but encountered problems in the process. After these issues, Intel moved to develop a successor to NetBurst, theCore microarchitecture, in 2006 after heat and other related problems started to pose an unbreakable barrier (inspired by the P6 Core of thePentium Pro to theTualatinPentium III-S, and most directly thePentium M.)

Intel replaced the originalWillamette core with a redesigned version of the NetBurst microarchitecture calledNorthwood in January 2002. TheNorthwood design combined an increased cache size, a smaller 130 nm fabrication process, andHyper-threading (although initially all models but the 3.06 GHz model had this feature disabled) to produce a more modern, higher-performing version of the NetBurst microarchitecture.

In February 2004, Intel introducedPrescott, a more radical revision of the microarchitecture. ThePrescott core was produced on a 90 nm process, and included several major design changes, including the addition of an even larger cache (from 512 KB in theNorthwood to 1 MB, and 2 MB in Prescott 2M), a much deeperinstruction pipeline (31 stages as compared to 20 in theNorthwood), a heavily improvedbranch predictor, the introduction of theSSE3 instructions, and later, the implementation of Intel Extended Memory 64 Technology (EM64T), Intel's branding for their compatible implementation of thex86-64 64-bit version of thex86 microarchitecture (as with hyper-threading, allPrescott chips branded Pentium 4 HT have hardware to support this feature, but it was initially only enabled on the high-endXeon processors, before being officially introduced in processors with thePentium trademark). Power consumption and heat dissipation also became major issues withPrescott, which quickly became the hottest-running, and most power-hungry, of Intel's single-core x86 and x86-64 processors. Power and heat concerns prevented Intel from releasing a Prescott clocked above 3.8 GHz, along with a mobile version of the core clocked above 3.46 GHz.

Intel also released a dual-core processor based on the NetBurst microarchitecture branded Pentium D. The first Pentium D core was codenamedSmithfield, which is actually two Prescott cores in a single die, and laterPresler, which consists of twoCedar Mill cores on two separate dies (Cedar Mill being the 65 nm die-shrink ofPrescott).

Intel had NetBurst-based successors in development calledTejas and Jayhawk with between 40 and 50 pipeline stages, but ultimately decided to replace NetBurst with theCore microarchitecture,^[8][9] released in July 2006; these successors were more directly derived from thePentium Pro (P6 microarchitecture). August 8, 2008 marked the end of Intel NetBurst-based processors.^[10] The reason for NetBurst's abandonment was the severe heat problems caused by high clock speeds. While some Core- and Nehalem-based processors have higherTDPs, most processors are multi-core, so each core gives off a fraction of the maximum TDP, and the highest-clocked Core-based single-core processors give off a maximum of 27 W of heat. The fastest-clocked desktop Pentium 4 processors (single-core) had TDPs of 115 W, compared to 88 W for the fastest clocked mobile versions. Although, with the introduction of new steppings, TDPs for some models were eventually lowered.

The Nehalem microarchitecture, the successor to the Core microarchitecture, was supposed to be an evolution of NetBurst according to Intel roadmaps dating back to 2000.^{[citation needed]} Nehalem reimplements certain features of NetBurst, including the Hyper-Threading technology first introduced in the 3.06 GHzNorthwood core, and L3 cache, first implemented on a consumer processor in theGallatin core used in the Pentium 4 Extreme Edition.

• Megahertz myth
• List of Intel CPU microarchitectures
• List of Intel Celeron processors (NetBurst-based)
• List of Intel Pentium 4 processors
• List of Intel Pentium D processors
• List of Intel Xeon processors (NetBurst-based)
• Tick–tock model

• The Microarchitecture of the Pentium 4 Processor

• Intel x86 microprocessors
• Intel microarchitectures
• X86 microarchitectures
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