 | |
| General information | |
|---|---|
| Common manufacturer | |
| Performance | |
| Max.CPUclock rate | 0.985 MHz to 1.023 MHz |
| Data width | 8 |
| Address width | 16 |
| Architecture and classification | |
| Instruction set | MOS 6502 |
| Physical specifications | |
| Package |
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| Products, models, variants | |
| Variant |
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| History | |
| Predecessor | MOS 6502 |
| Successor | MOS 8502 |
TheMOS Technology 6510 is an8-bitmicroprocessor designed byMOS Technology. It is a modified form of the very successful6502. The 6510 is widely used in theCommodore 64 (C64)home computer and its variants. It is also used in the Seagate ST-251 MFM hard disk.[1]
The primary change from the 6502 is the addition of an 8-bit general purposeI/O port, although only 6 I/O pins are available in the most common version of the 6510. In addition, the address bus can be madetri-state and the CPU can be halted cleanly.
The 6510 and variants were based on the same core as the 6502, and areopcode compatible, includingundocumented opcodes.[2]
The parallel port was provided by using several formerly unused pins, eliminating some, and re-arranging others. In the original 6502, pins 5, 35 and 36 were not connected. Pin 3, formerly the phase-1 clock out, was eliminated, as most roles did not require it. This left only CLKIN, moved to pin 1 from 37, and CLKOUT on its original pin 39. The SO pin, which was connected to the overflow flag in the processor status register, was eliminated as few applications made use of it and the new parallel port could provide similar functionality. The final pin to be removed was the VSS on pin 1, the original 6520 had it on both pin 1 and pin 21, on the opposite side of the chip, but only one was needed.
The pins were also re-arranged. The VSS (ground) on pin 1 became clock in, while the other pins on the right side all moved up to fill the space from the removed clock out on pin 3 and unused pin 5. This putaddress bus pins A0 to A13 on one side, instead of 0 through 11 on the 6502, removing two from the left side. On the left side, the SO and two unconnected pins were removed, while clock in moved to pin 1 and the two address pins to 19 and 20, leaving pins 29 through 24 to be available for the parallel port pins, P0 through P5.
In the C64, the extra I/O pins of the processor are used to control the computer'smemory map bybank switching, and for controlling three of the four signal lines of theDatasette tape recorder (the electric motor control, key-press sensing and write data lines; the read data line went to another I/O chip). It is possible, by writing the correctbit pattern to the processor at address $01, to completely expose almost the full 64 KB ofRAM in the C64, leaving noROM orI/O hardware exposed except for the processor I/O port itself and its data directional register at address $00.[3]
In 1985, MOS produced the8500, anHMOS version of the 6510. Other than the process modification, it is virtually identical to theNMOS version of the 6510. The 8500 was originally designed for use in the modernised C64, the C64C. However, in 1985, limited quantities of 8500s were found on older NMOS-based C64s. It finally made its official debut in 1987, appearing in a motherboard using the new 85xx HMOS chipset.
The7501/8501 variant of the 6510 was introduced in 1984.[4] Compared to the 6510, this variant extends the number of I/O port pins from 6 to 8, but omits the pins for non-maskable interrupt and clock output.[5] It is used in Commodore'sC16,C116 andPlus/4 home computers, where its I/O port controls not only theDatasette but also theCBM Bus interface. The main difference between 7501 and 8501 CPUs is that they were manufactured with slightly different processes: 7501 was manufactured withHMOS-1 and 8501 with HMOS-2.[4]
The 2 MHz-capable8502 variant is used in theCommodore 128.
TheCommodore 1551 disk drive (for theCommodore Plus/4) uses the6510T, a version of the 6510 with eight I/O lines. TheNMI and RDY signals are not available.