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Amultigate device,multi-gate MOSFET ormulti-gate field-effect transistor (MuGFET) refers to ametal–oxide–semiconductor field-effect transistor (MOSFET) that has more than onegate on a single transistor. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called amultiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are theFinFET (fin field-effect transistor) and theGAAFET (gate-all-around field-effect transistor), which are non-planar transistors, or3D transistors.
Multi-gatetransistors are one of the several strategies being developed byMOSsemiconductor manufacturers to create ever-smallermicroprocessors andmemory cells, colloquially referred to as extendingMoore's law (in its narrow, specific version concerning density scaling, exclusive of its careless historical conflation withDennard scaling).[1] Development efforts into multigate transistors have been reported by theElectrotechnical Laboratory,Toshiba,Grenoble INP,Hitachi,IBM,TSMC,UC Berkeley,Infineon Technologies,Intel,AMD,Samsung Electronics,KAIST,Freescale Semiconductor, and others, and theITRS predicted correctly that such devices will be the cornerstone ofsub-32 nm technologies.[2] The primary roadblock to widespread implementation is manufacturability, as bothplanar and non-planar designs present significant challenges, especially with respect tolithography and patterning. Other complementary strategies for device scaling include channelstrain engineering,silicon-on-insulator-based technologies, andhigh-κ/metal gate materials.
Dual-gate MOSFETs are commonly used invery high frequency (VHF) mixers and in sensitive VHF front-end amplifiers. They are available from manufacturers such asMotorola,NXP Semiconductors, andHitachi.[3][4][5]
Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and the number of channels/gates (2, 3, or 4).
A planar double-gate MOSFET (DGMOS) employs conventionalplanar (layer-by-layer) manufacturing processes to create double-gateMOSFET (metal–oxide–semiconductor field-effect transistor) devices, avoiding more stringentlithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the drain–source channel is sandwiched between two independently fabricated gate/gate-oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.[6]
FlexFET is a planar, independently double-gated transistor with adamascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. FlexFET is a true double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and (2) the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa.[7] FlexFET was developed and is manufactured by American Semiconductor, Inc.
FinFET (fin field-effect transistor) is a type of non-planar transistor, or "3D" transistor (not to be confused with3D microchips).[8] The FinFET is a variation on traditional MOSFETs distinguished by the presence of a thin silicon "fin" inversion channel on top of the substrate, allowing the gate to make two points of contact: the left and right sides of the fin. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming othershort-channel effects.
The first FinFET transistor type was called a "Depleted Lean-channel Transistor" or "DELTA" transistor, which was firstfabricated byHitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[9][10][11] In the late 1990s, Digh Hisamoto began collaborating with an international team of researchers on further developing DELTA technology, includingTSMC'sChenming Hu and aUC Berkeley research team includingTsu-Jae King Liu,Jeffrey Bokor, Xuejue Huang, Leland Chang, Nick Lindert, S. Ahmed, Cyrus Tabery, Yang-Kyu Choi, Pushkar Ranade, Sriram Balasubramanian, A. Agarwal and M. Ameen. In 1998, the team developed the firstN-channel FinFETs and successfully fabricated devices down to a17 nm process. The following year, they developed the firstP-channel FinFETs.[12] They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper.[13]
In current usage the term FinFET has a less precise definition. Amongmicroprocessor manufacturers,AMD,IBM, andFreescale describe their double-gate development efforts as FinFET[14] development, whereasIntel avoids using the term when describing their closely related tri-gate architecture.[15] In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one, to increase drive strength and performance.[16] The gate may also cover the entirety of the fin(s).
A 25 nm transistor operating on just 0.7 volt was demonstrated in December 2002 byTSMC (Taiwan Semiconductor Manufacturing Company). The "Omega FinFET" design is named after the similarity between the Greek letteromega (Ω) and the shape in which the gate wraps around the source/drain structure. It has agate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.
In 2004,Samsung Electronics demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamicrandom-access memory (DRAM) manufactured with a90 nm Bulk FinFET process.[12] In 2006, a team of Korean researchers from theKorea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a3 nm transistor, the world's smallestnanoelectronic device, based on FinFET technology.[17][18] In 2011,Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[19]
In 2012, Intel started using FinFETs for its future commercial devices. Leaks suggest that Intel's FinFET has an unusual shape of a triangle rather than rectangle, and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area-to-volume ratio than a rectangular prism, thus increasing switching performance.[20]
In September 2012,GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014.[21] The next month, the rival companyTSMC announced start early or "risk" production of 16 nm FinFETs in November 2013.[22]
In March 2014,TSMC announced that it is nearing implementation of several16 nm FinFETsdie-onwafersmanufacturingprocesses:[23]
AMD released GPUs using their Polaris chip architecture and made on 14 nm FinFET in June 2016.[24] The company has tried to produce a design to provide a "generational jump in power efficiency" while also offering stable frame rates for graphics, gaming, virtual reality, and multimedia applications.[25]
In March 2017,Samsung andeSilicon announced thetapeout for production of a 14 nm FinFET ASIC in a 2.5D package.[26][27]
Atri-gate transistor, also known as a triple-gate transistor, is a type of MOSFET with a gate on three of its sides.[28] A triple-gate transistor was first demonstrated in 1987, by aToshiba research team including K. Hieda, Fumio Horiguchi and H. Watanabe. They realized that the fully depleted (FD) body of a narrow bulkSi-based transistor helped improve switching due to a reduced body-bias effect.[29][30] In 1992, a triple-gate MOSFET was demonstrated byIBM researcher Hon-Sum Wong.[31]
Intel announced this technology in September 2002.[32] Intel announced "triple-gate transistors" which maximize "transistor switching performance and decreases power-wasting leakage". A year later, in September 2003,AMD announced that it was working on similar technology at the International Conference on Solid State Devices and Materials.[33][34] No further announcements of this technology were made until Intel's announcement in May 2011, although it was stated at IDF 2011, that they demonstrated a workingSRAM chip based on this technology at IDF 2009.[35]
On April 23, 2012, Intel released a new line of CPUs, termedIvy Bridge, which feature tri-gate transistors.[36][37] Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass-production issues. The new style of transistor was described on May 4, 2011, in San Francisco.[38] It was announced that Intel's factories were expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs.[39] It was announced that the new transistors would also be used in Intel'sAtom chips for low-powered devices.[38]
Tri-gate fabrication was used byIntel for the non-planar transistor architecture used inIvy Bridge,Haswell andSkylake processors. These transistors employ a single gate stacked on top of two vertical gates (a single gate wrapped over three sides of the channel), allowing essentially three times the surface area forelectrons to travel. Intel reports that their tri-gate transistors reduceleakage and consume far lesspower than previous transistors. This allows up to 37% higher speed or a power consumption at under 50% of the previous type of transistors used by Intel.[40][41]
Intel explains: "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)."[42] Intel has stated that all products afterSandy Bridge will be based upon this design.
The termtri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels.[43]
Gate-all-around FETs (GAAFETs) are the successor to FinFETs, as they can work at sizes below 7 nm. They were used by IBM to demonstrate5 nm process technology.
GAAFET, also known as a surrounding-gate transistor (SGT),[44][45] is similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully characterized both theoretically and experimentally.[46][47] They have also been successfully etched ontonanowires ofInGaAs, which have a higherelectron mobility than silicon.[48]
A gate-all-around (GAA) MOSFET was first demonstrated in 1988, by aToshiba research team includingFujio Masuoka, Hiroshi Takato, and Kazumasa Sunouchi, who demonstrated a vertical nanowire GAAFET which they called a "surrounding gate transistor" (SGT).[49][50][45] Masuoka, best known as the inventor offlash memory, later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along withTohoku University.[51] In 2006, a team of Korean researchers from theKorea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a3 nm transistor, the world's smallestnanoelectronic device, based on gate-all-around (GAA) FinFET technology.[52][18] GAAFET transistors may make use of high-k/metal gate materials. GAAFETs with up to 7nanosheets have been demonstrated which allow for improved performance and/or reduced device footprint. The widths of the nanosheets in GAAFETs is controllable which more easily allows for the adjustment of device characteristics.[53]
As of 2020, Samsung and Intel have announced plans to mass produce GAAFET transistors (specifically MBCFET transistors) while TSMC has announced that they will continue to use FinFETs in their 3 nm node,[54] despite TSMC developing GAAFET transistors.[55]
A multi-bridge channel FET (MBCFET) is similar to a GAAFET except for the use of nanosheets instead of nanowires.[56] MBCFET is a word mark (trademark) registered in the U.S. to Samsung Electronics.[57] Samsung plans on mass producing MBCFET transistors at the3 nm node for its foundry customers.[58] Intel is also developing RibbonFET, a variation of MBCFET "nanoribbon" transistors.[59][60] Unlike FinFETs, both the width and the number of the sheets can be varied to adjust drive strength or the amount of current the transistor can drive at a given voltage. The sheets often vary from 8 to 50 nanometers in width. The width of the nanosheets is known as Weff, or effective width.[61][62]
Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from the undesirable short-channel effect, especially "off-state" leakage current, which increases the idle power required by the device.[63]
In a multigate device, the channel is surrounded by several gates on multiple surfaces. Thus it provides better electrical control over the channel, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. Multigate transistors also provide a better analog performance due to a higher intrinsic gain and lower channel length modulation.[64] These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics.
The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include:
BSIMCMG106.0.0,[65] officially released on March 1, 2012 by UC BerkeleyBSIM Group, is the first standard model for FinFETs. BSIM-CMG is implemented inVerilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with the 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD = 1).
All of the important multi-gate (MG) transistor behavior is captured by this model. Volume inversion is included in the solution ofPoisson's equation, hence the subsequent I–V formulation automatically captures the volume-inversion effect. Analysis of electrostatic potential in the body of MG MOSFETs provided a model equation for short-channel effects (SCE). The extra electrostatic control from the end gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short-channel model.
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