M·CORE is a low-power,RISC-basedmicrocontrollerarchitecture developed byMotorola (subsequentlyFreescale, now part ofNXP), intended for use inembedded systems. Introduced in late 1997, the architecture combines a32-bit internal data path with16-bit instructions,[1] and includes a four-stageinstruction pipeline. Initial implementations used a 360nm process and ran at 50 MHz.
M·CORE processors[2] employ avon Neumann architecture with shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to havelow power consumption and highcode density.[3]
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