Alow-dropout regulator (LDO regulator) is a type of a DClinear voltage regulator circuit that can operate even when the supply voltage is very close to the output voltage.^[1]The advantages of an LDO regulator over other DC-to-DCvoltage regulators include: the absence of switching noise (in contrast toswitching regulators); smaller device size (as neither large inductors nor transformers are needed); and greater design simplicity (usually consists of areference, anamplifier, and a pass element). The disadvantage is that linear DC regulators mustdissipate heat in order to operate.^[2]

The adjustable low-dropout regulator debuted on April 12, 1977 in anElectronic Design article entitled "Break Loose from Fixed IC Regulators". The article was written byRobert Dobkin, anIC designer then working forNational Semiconductor. Because of this, National Semiconductor claims the title of "LDO inventor".^[3] Dobkin later left National Semiconductor in 1981 and foundedLinear Technology where he was the chief technology officer.^[4]

The main components are a powerFET and adifferential amplifier (error amplifier). One input of the differential amplifier monitors the fraction of the output determined by theresistor ratio of R1 and R2. The second input to the differential amplifier is from a stable voltage reference (bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the power FET changes to maintain a constant output voltage.

Low-dropout (LDO) regulators operate similarly to alllinear voltage regulators. The main difference between LDO and non-LDO regulators is their schematictopology. Instead of anemitter follower topology, low-dropout regulators consist of anopen collector or open drain topology, where the transistor may be easily driven intosaturation with the voltages available to the regulator. This allows the voltage drop from the unregulated voltage to the regulated voltage to be as low as the saturation voltage across the transistor.^{[2]: Appendix A}

In Fig. 1, the opamp's non-inverting input will have a voltage of:

${\displaystyle V_{\text{-}}=\frac{R_2}{R_1+R_2}{V}_{\text{out}}.}$

When this voltage is less than Vref, the opamp will turn on the pass element. The feedback loop keeps${\displaystyle V_{\text{-}}}$ about equal to${\displaystyle V_{\text{ref}}.}$ Solving for the output voltage yields:

${\displaystyle V_{\text{out}}=\left(1+\frac{R_1}{R_2}\right)V_{\text{ref}}.}$

If abipolar transistor is used, as opposed to afield-effect transistor orJFET, significant additional power may be lost to control it, whereas non-LDO regulators take that power from voltage drop itself. For high voltages under very low V_in-V_out difference there will be significant power loss in the control circuit.^[5]

Because the power control element is an inverter, another inverting amplifier is required to control it, increasing circuit complexity compared to simplelinear regulator.^{[citation needed]}

PowerFETs may be preferable in order to reduce power consumption, yet this poses problems when the regulator is used for low input voltage, since FETs usually require 5 to 10 V to close completely. Power FETs may also increase the cost.

The power dissipated in the pass element and internal circuitry (${\displaystyle P_{\text{LOSS}}}$) of a typical LDO is calculated as follows:

${\displaystyle P_{\text{LOSS}}=\left(V_{\text{IN}}-V_{\text{OUT}}\right)I_{\text{OUT}}+V_{\text{IN}}{I}_{\text{Q}}}$

where${\displaystyle I_{\text{Q}}}$ is the quiescent current required by the LDO for its internal circuitry.

Therefore, one can calculate the efficiency as follows:

${\displaystyle \eta =\frac{P_{\text{IN}}-P_{\text{LOSS}}}{P_{\text{IN}}}}$   where  ${\displaystyle P_{\text{IN}}=V_{\text{IN}}{I}_{\text{IN}}}$

However, when the LDO is in full operation (i.e., supplying current to the load) generally:${\displaystyle I_{\text{OUT}}\gg I_{\text{Q}}}$. This allows us to reduce${\displaystyle P_{\text{LOSS}}}$ to the following:

${\displaystyle P_{\text{LOSS}}=\left(V_{\text{IN}}-V_{\text{OUT}}\right)I_{\text{OUT}}}$

which further reduces the efficiency equation to:

${\displaystyle \eta =\frac{V_{\text{OUT}}}{V_{\text{IN}}}}$

It is important to keep thermal considerations in mind when using a low drop-out linear regulator. Having high current and/or a wide differential between input and output voltage could lead to large power dissipation. Additionally,efficiency will suffer as the differential widens. Depending on thepackage, excessive power dissipation could damage the LDO or cause it to go into thermal shutdown.

Among other important characteristics of a linear regulator is thequiescent current, also known as ground current or supply current, which accounts for the difference, although small, between the input and output currents of the LDO, that is:

${\displaystyle I_{\text{Q}}=I_{\text{IN}}-I_{\text{OUT}}}$

Quiescent current is current drawn by the LDO in order to control its internal circuitry for proper operation. The series pass element,topologies, and ambient temperature are the primary contributors to quiescent current.^[6]

Many applications do not require an LDO to be in full operation all of the time (i.e. supplying current to the load). In this idle state the LDO still draws a small amount of quiescent current in order to keep the internal circuitry ready in case a load is presented. When no current is being supplied to the load,${\displaystyle P_{\text{LOSS}}}$ can be found as follows:

${\displaystyle P_{\text{LOSS}}=V_{\text{IN}}{I}_Q}$

In addition to regulating voltage, LDOs can also be used asfilters. This is especially useful when a system is usingswitchers, which introduce aripple in the output voltage occurring at the switching frequency. Left alone, this ripple has the potential to adversely affect the performance ofoscillators,^[7]data converters,^[8] and RF systems^[9] being powered by the switcher. However, any power source, not just switchers, can contain AC elements that may be undesirable for design.

Two specifications that should be considered when using an LDO as a filter are power supply rejection ratio (PSRR) and output noise.

An LDO is characterized by its drop-out voltage, quiescent current, load regulation, line regulation, maximum current (which is decided by the size of the pass transistor), speed (how fast it can respond as the load varies), voltage variations in the output because of sudden transients in the load current, outputcapacitor and its equivalent series resistance.^[10] Speed is indicated by therise time of the current at the output as it varies from 0 mA load current (no load) to the maximum load current. This is basically decided by the bandwidth of the error amplifier. It is also expected from an LDO to provide a quiet and stable output in all circumstances (example of possible perturbation could be: sudden change of the input voltage or output current). Stability analysis put in place some performance metrics to get such a behaviour and involve placing poles and zeros appropriately. Most of the time, there is a dominant pole that arise at low frequencies while other poles and zeros are pushed at high frequencies.

PSRR refers to the LDO's ability to reject ripple it sees at its input.^[11] As part of its regulation, the error amplifier and bandgap reference attenuate any spikes in the input voltage that deviate from the internal reference to which it is compared.^[12] In an ideal LDO, the output voltage would be solely composed of the DC frequency. However, the error amplifier is limited in its ability to gain small spikes at high frequencies. PSRR is expressed as follows:^[11]

${\displaystyle \text{PSRR}=\frac{\mathrm{\Delta }{V}_{\text{IN}}^2}{\mathrm{\Delta }{V}_{\text{OUT}}^2}=10\log \left(\frac{\mathrm{\Delta }{V}_{\text{IN}}^2}{\mathrm{\Delta }{V}_{\text{OUT}}^2}\right)\text{dB}}$

As an example, an LDO that has a PSRR of 55 dB at 1 MHz attenuates a 1 mV input ripple at this frequency to just 1.78 μV at the output. A 6 dB increase in PSRR roughly equates to an increase in attenuation by a factor of 2.

Most LDOs have relatively high PSRR at lower frequencies (10 Hz – 1 kHz). However, a Performance LDO is distinguished in having high PSRR over a broad frequency spectrum (10 Hz – 5 MHz). Having high PSRR over a wide band allows the LDO to reject high-frequency noise like that arising from a switcher. Similar to other specifications, PSRR fluctuates over frequency, temperature, current, output voltage, and the voltage differential.

The noise from the LDO itself must also be considered in filter design. Like other electronic devices, LDOs are affected bythermal noise, bipolarshot noise, andflicker noise.^[9] Each of these phenomena contributes noise to the output voltage, mostly concentrated over the lower end of the frequency spectrum. In order to properly filter AC frequencies, an LDO must both reject ripple at the input while introducing minimal noise at the output. Efforts to attenuate ripple from the input voltage could be in vain if a noisy LDO just adds that noise back again at the output.

Load regulation is a measure of the circuit's ability to maintain the specified output voltage under varying load conditions. Load regulation is defined as:

${\displaystyle \text{Load Regulation}=\frac{\mathrm{\Delta }{V}_{\text{OUT}}}{\mathrm{\Delta }{I}_{\text{OUT}}}}$

The worst case of the output voltage variations occurs as the load current transitions from zeroto its maximum rated value or vice versa.^[6]

Line regulation is a measure of the circuit's ability to maintain the specified outputvoltage with varying input voltage. Line regulation is defined as:

${\displaystyle \text{Line regulation}=\frac{\mathrm{\Delta }{V}_{\text{OUT}}}{\mathrm{\Delta }{V}_{\text{IN}}}}$

Like load regulation, line regulation is a steady state parameter—all frequency components are neglected. Increasing DC open-loop current gain improves the line regulation.^[6]

The transient response is the maximum allowable output voltage variation for a load current step change. The transient response is a function of the output capacitor value ($C_{\text{OUT}}$), the equivalent series resistance (ESR) of the output capacitor, the bypass capacitor ($C_{\text{BYP}}$) that is usually added to the output capacitor to improve the load transient response, and the maximum load-current ($I_{\text{OUT,MAX}}$). The maximum transient voltage variation is defined as follows:

${\displaystyle \mathrm{\Delta }{V}_{\text{TR,MAX}}=\frac{I_{\text{OUT,MAX}}}{C_{\text{OUT}}+C_{\text{BYP}}}\mathrm{\Delta }{t}_1+\mathrm{\Delta }{V}_{\text{ESR}}}$^[6]

Where$\mathrm{\Delta }{t}_1$ corresponds to the closed-loop bandwidth of an LDO regulator.$\mathrm{\Delta }{V}_{\text{ESR}}$ is the voltage variation resulting from the presence of the ESR ($R_{\text{ESR}}$) of the output capacitor. The application determines how low this value should be.

• Linear regulator
• Low-voltage detect (sometimes confused with LDO regulator)
• Voltage regulator
• Voltage regulator module
• Switched-mode power supply
• List of linear integrated circuits
• LM7805

• Understanding Low Dropout Regulators - Basics
• Understanding LDO Regulators - TI
• Understanding Noise and PSRR in LDOs - All About Circuits
• Understanding Noise in LDOs - TI
• Index of TI LDO Application Notes - TI

• Voltage regulation
• Linear integrated circuits

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