 An Intel P8085AH-2 processor variant with black plastic and silver pins | |
| General information | |
|---|---|
| Launched | March 1976 |
| Discontinued | 2000[1] |
| Common manufacturer |
|
| Performance | |
| Max.CPUclock rate | 3, 5 and 6 MHz |
| Data width | 8 bits |
| Address width | 16 bits |
| Architecture and classification | |
| Technology node | 3 μm |
| Instruction set | 8085 |
| Physical specifications | |
| Transistors |
|
| Package |
|
| Socket | |
| History | |
| Predecessor | Intel 8080 |
| Successor | Intel 8086 |
| Support status | |
| Unsupported | |
The Intel 8085 ("eighty-eighty-five") is an8-bitmicroprocessor produced byIntel and introduced in March 1976.[2] It isbinary compatible with the more famousIntel 8080. It is the last 8-bit microprocessor developed by Intel. The "5" in the part number highlighted the fact that the 8085 uses a single +5-volt (V) power supply, compared to the 8080's +5, −5, and +12 V, which makes the 8085 easier to integrate into systems that by this time were mostly +5 V.
The other major change was the addition of four new interrupt pins and aserial port, with separate input and output pins. This was often all that was needed in simple systems and eliminated the need for separateintegrated circuits to provide this functionality, as well as simplifying thecomputer bus as a result. The only changes in theinstruction set compared to the 8080 were instructions for reading and writing data using these pins.
The 8085 is supplied in a 40-pinDIP package. Given the new pins, this requiredmultiplexing 8-bits of the address (AD0–AD7) bus with the data bus. This means that specifying a complete 16-bit address requires it to be sent via two 8-bit pathways, and one of those two has to be temporarily latched using separate hardware such as a74LS373. Intel manufactured several support chips with an address latch built in. These include the 8755, with an address latch, 2 KB ofEPROM and 16 I/O pins, and the 8155 with 256 bytes ofRAM, 22 I/O pins and a 14-bit programmable timer/counter. The multiplexed address/data bus reduced the number of PCB tracks between the 8085 and such memory and I/O chips.
While the 8085 was an improvement on the 8080, it was eclipsed by theZilog Z80 in the late 1970s and early 1980s, which took over much of the desktop computer market.
Although not widely used in computers, the 8085 had a long life as a microcontroller. Once designed into such products as theDECtape II controller and theVT102 video terminal in the late 1970s, the 8085 served for new production throughout the lifetime of those products.
The 8085 is a conventionalvon Neumann design based on the Intel 8080. Unlike the 8080 it does not multiplex state signals onto the data bus, but the 8-bitdata bus is instead multiplexed with the lower eight bits of the 16-bitaddress bus to limit the number of pins to 40. State signals are provided by dedicated bus control signal pins and two dedicated bus state ID pins named S0 and S1. Pin 40 is used for the power supply (+5 V) and pin 20 for ground. Pin 39 is used as the Hold pin.
The Intel 8085 processor was designed usingnMOS circuitry, with later "H" versions implemented in Intel's enhanced nMOS process known asHMOS II ("High-performance MOS"), which was originally developed for fast static RAM products.[3] Unlike the 8080, the 8085 requires only a single 5-volt power supply, similar to its competing processors. The 8085 contains approximately 6,500transistors.[4]
The 8085 incorporates the functions of the 8224 (clock generator) and the 8228 (system controller) on chip, increasing the level of integration. A downside compared to similar contemporary designs (such as the Z80) is the fact that the buses require demultiplexing; however, address latches in the Intel 8155, 8355, and 8755 memory chips allow a direct interface, so an 8085 along with these chips is almost a complete system.
The 8085 has extensions to support newinterrupts, with three maskable vectored interrupts (RST 7.5, RST 6.5 and RST 5.5), onenon-maskable interrupt (TRAP), and one externally serviced interrupt (INTR). Each of these five interrupts has a separate pin on the processor, a feature which permits simple systems to avoid the cost of a separate interrupt controller. The RST 7.5 interrupt is edge triggered (latched), while RST 5.5 and 6.5 are level-sensitive. All interrupts except TRAP are enabled by the EI instruction and disabled by the DI instruction. In addition, the SIM (Set Interrupt Mask) and RIM (Read Interrupt Mask) instructions, the only instructions of the 8085 that are not from the 8080 design, allow each of the three maskable RST interrupts to be individually masked. All three are masked after a normal CPU reset. SIM and RIM also allow the global interrupt mask state and the three independent RST interrupt mask states to be read, the pending-interrupt states of those same three interrupts to be read, the RST 7.5 trigger-latch flip-flop to be reset (cancelling the pending interrupt without servicing it), and serial data to be sent and received via the SOD and SID pins, respectively, all under program control and independently of each other.
SIM and RIM each execute in four clock cycles (T states), making it possible to sample SID and/or toggle SOD considerably faster than it is possible to toggle or sample a signal via any I/O or memory-mapped port, e.g. one of the ports of an 8155. (In this way, SID can be compared to the SO ["Set Overflow"] pin of the 6502 CPU contemporary to the 8085.)
Like the 8080, the 8085 can accommodate slower memories through externally generatedwait states (pin 35, READY), and has provisions forDirect Memory Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over the 8080 is that the 8085 can itself drive apiezoelectric crystal directly connected to it, and a built-in clock generator generates the internal high-amplitudetwo-phase clock signals at half the crystal frequency (a 6.14 MHz crystal would yield a 3.07 MHz clock, for instance). The internal clock is available on an output pin, to drive peripheral devices or other CPUs in lock-step synchrony with the CPU from which the signal is output. The 8085 can also be clocked by an externaloscillator (making it feasible to use the 8085 in synchronous multi-processor systems using a system-wide common clock for all CPUs, or to synchronize the CPU to an external time reference such as that from a video source or a high-precision time reference).
The 8085 is abinary compatible follow-up on the 8080. It supports the completeinstruction set of the 8080, with exactly the same instruction behavior, including all effects on the CPU flags (except for the AND/ANI operation, which sets the AC flag differently).[5] This means that the vast majority of object code (any program image in ROM or RAM) that runs successfully on the 8080 can run directly on the 8085 without translation or modification. (Exceptions include timing-critical code and code that is sensitive to the aforementioned difference in the AC flag setting or differences in undocumented CPU behavior.) 8085 instruction timings differ slightly from the 8080—some 8-bit operations, including INR, DCR, and the heavily used MOV r,r instructions, are one clock cycle faster, but instructions that involve 16-bit operations, including stack PUSH (which decrements the 16-bit SP register) generally one cycle slower. Conditional jumps not taken are three clocks faster on the 8085. As mentioned already, only the SIM and RIM instructions were new to the 8085.[nb 1]
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The processor has seven 8-bitregisters accessible to the programmer, named A, B, C, D, E, H, and L, where A is also known as the accumulator. The other six registers can be used as independent byte-registers or as three 16-bit register pairs, BC, DE, and HL (or B, D, H, as referred to in Intel documents), depending on the particular instruction.
Some instructions use HL as a (limited) 16-bit accumulator. As in the 8080, the contents of the memory address pointed to by HL can be accessed as pseudo register M. It also has a 16-bitprogram counter and a 16-bitstack pointer to memory (replacing the 8008's internalstack). Instructions such as PUSH PSW, POP PSW affect the Program Status Word (accumulator and flags). The accumulator stores the results of arithmetic and logical operations, and the flags register bits (sign, zero, auxiliary carry, parity, and carry flags) are set or cleared according to the results of these operations. The sign flag is set if the result has a negative sign (i.e. it is set if bit 7 of the accumulator is set). The auxiliary or half carry flag is set if a carryover from bit 3 to bit 4 occurred. The parity flag is set to 1 if the parity (number of 1-bits) of the accumulator is even; if odd, it is cleared. The zero flag is set if the result of the operation was 0. Lastly, the carry flag is set if a carryover from bit 7 of the accumulator (the MSB) occurred.
As in many other 8-bit processors, all instructions are encoded in a single byte (including register-numbers, but excluding immediate data), for simplicity. Some of them are followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. A NOP "no operation" instruction exists, which does not modify any of the registers or flags. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns (which can be conditionally executed, like jumps) and instructions to save and restore any 16-bit register-pair on the machine stack. There are also eight one-byte call instructions (RST) for subroutines located at the fixed addresses 00h, 08h, 10h,...,38h. These are intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls. One sophisticated instruction is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.
All two-operand 8-bit arithmetic and logical (ALU) operations work on the 8-bitaccumulator (the A register). For two-operand 8-bit operations, the other operand can be either an immediate value, another 8-bit register, or a memory cell addressed by the 16-bit register pair HL. The only 8-bit ALU operations that can have a destination other than the accumulator are the unary incrementation or decrementation instructions, which can operate on any 8-bit register or on memory addressed by HL, as for two-operand 8-bit operations. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory cell, using the MOV instruction. An immediate value can also be moved into any of the foregoing destinations, using the MVI instruction. Due to the regular encoding of the MOV instruction (using nearly a quarter of the entire opcode space) there are redundant codes to copy a register into itself (MOV B,B, for instance), which are of little use, except for delays.[nb 2] However, what would have been a copy from the HL-addressed cell into itself (i.e.,MOV M,M) instead encodes theHLT instruction, halting execution until an external reset or unmasked interrupt occurs.[nb 3]
Although the 8085 is an 8-bit processor, it has some 16-bit operations. Any of the three 16-bit register pairs (BC, DE, HL) or SP can be loaded with an immediate 16-bit value (using LXI), incremented or decremented (using INX and DCX), or added to HL (using DAD). LHLD loads HL from directly addressed memory and SHLD stores HL likewise. The XCHG operation exchanges the values of HL and DE. XTHL exchanges last item pushed on stack with HL. Adding HL to itself performs a 16-bit arithmetic left shift with one instruction. The only 16-bit instruction that affects any flag is DAD (adding BC, DE, HL, or SP to HL), which updates the carry flag to facilitate 24-bit or larger additions and left shifts. Adding the stack pointer to HL is useful for indexing variables in (recursive) stack frames. A stack frame can be allocated using DAD SP and SPHL, and a branch to a computed pointer can be done with PCHL. These abilities make it feasible to compile languages such asPL/M,Pascal, orC with 16-bit variables and produce 8085 machine code. Subtraction and bitwise logical operations on 16 bits is done in 8-bit steps. Operations that have to be implemented by program code (subroutine libraries) include comparisons of signed integers as well as multiplication and division.
A number of undocumented instructions and flags were discovered by two software engineers, Wolfgang Dehnhardt and Villy M. Sorensen in the process of developing an 8085 assembler. These instructions use 16-bit operands and include indirect loading and storing of a word, a subtraction, a shift, a rotate, and offset operations.[6]
By the time 8085 was designed but not yet announced, many designers found it to be inferior to the competing products already on the market. The next generation 16-bit 8086 CPU was already in development. Intel made a last minute decision to leave 10 out of 12 new 8085 instructions undocumented to speed up and simplify the design of the upcoming 8086 CPU.[7]
Differences between the 8080 and the 8085 arehighlighted. Compared to the 8080, the 8085 may take more clocks↑, fewer clocks↓, or a mixture↕. For explanations of some symbols, see lower part of the table.
| Opcode | Operands | Mnemonic | Clocks | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | — | NOP | 4 | No operation |
| 0 | 0 | RP | 0 | 0 | 0 | 1 | datlo | dathi | LXIrp,data | 10 | RP ←data | |
| 0 | 0 | RP | 0 | 0 | 1 | 0 | — | — | STAXrp | 7 | (RP) ← A [BC or DE only] | |
| 0 | 0 | RP | 0 | 0 | 1 | 1 | — | — | INXrp | 6 ↑ | RP ← RP + 1 | |
| 0 | 0 | DDD | 1 | 0 | 0 | — | — | INRddd | 4/10 ↓ | DDD ← DDD + 1 | ||
| 0 | 0 | DDD | 1 | 0 | 1 | — | — | DCRddd | 4/10 ↓ | DDD ← DDD - 1 | ||
| 0 | 0 | DDD | 1 | 1 | 0 | data | — | MVIddd,data | 7/10 | DDD ← data | ||
| 0 | 0 | RP | 1 | 0 | 0 | 1 | — | — | DADrp | 10 | HL ← HL + RP | |
| 0 | 0 | RP | 1 | 0 | 1 | 0 | — | — | LDAXrp | 7 | A ← (RP) [BC or DE only] | |
| 0 | 0 | RP | 1 | 0 | 1 | 1 | — | — | DCXrp | 6 ↑ | RP ← RP - 1 | |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | RLC | 4 | A1-7 ← A0-6; A0 ← Cy ← A7 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | RRC | 4 | A0-6 ← A1-7; A7 ← Cy ← A0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | RAL | 4 | A1-7 ← A0-6; Cy ← A7; A0 ← Cy |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | RAR | 4 | A0-6 ← A1-7; Cy ← A0; A7 ← Cy |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | — | — | RIM | 4 | A ← interrupt mask |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | addlo | addhi | SHLDadd | 16 | (add) ← HL |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | DAA | 4 | If A0-3 > 9 OR AC = 1 then A ← A + 6; then if A4-7 > 9 OR Cy = 1 then A ← A + 0x60 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | addlo | addhi | LHLDadd | 16 | HL ← (add) |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | CMA | 4 | A ← ¬A |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | — | — | SIM | 4 | interrupt mask ← A |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | addlo | addhi | STAadd | 13 | (add) ← A |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | — | — | STC | 4 | Cy ← 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | addlo | addhi | LDAadd | 13 | A ← (add) |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | CMC | 4 | Cy ← ¬Cy |
| 0 | 1 | DDD | SSS | — | — | MOVddd,sss | 4/7 ↓ | DDD ← SSS | ||||
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | HLT | 5 ↓ | Halt |
| 1 | 0 | ALU | SSS | — | — | ADD ADC SUB SBB ANA XRA ORA CMPsss | 4/7 | A ← A [ALU operation] SSS | ||||
| 1 | 1 | CC | 0 | 0 | 0 | — | — | Rcc (RET conditional) | 6/12 ↑ | If cc true, PC ← (SP), SP ← SP + 2 | ||
| 1 | 1 | RP | 0 | 0 | 0 | 1 | — | — | POPrp | 10 | RP ← (SP), SP ← SP + 2 | |
| 1 | 1 | CC | 0 | 1 | 0 | addlo | addhi | Jccadd (JMP conditional) | 7/10 ↓ | If cc true, PC ← add | ||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | addlo | addhi | JMPadd | 10 | PC ← add |
| 1 | 1 | CC | 1 | 0 | 0 | addlo | addhi | Cccadd (CALL conditional) | 9/18 ↕ | If cc true, SP ← SP - 2, (SP) ← PC, PC ← add | ||
| 1 | 1 | RP | 0 | 1 | 0 | 1 | — | — | PUSHrp | 12 ↑ | SP ← SP - 2, (SP) ← RP | |
| 1 | 1 | ALU | 1 | 1 | 0 | data | — | ADI ACI SUI SBI ANI XRI ORI CPIdata | 7 | A ← A [ALU operation] data | ||
| 1 | 1 | N | 1 | 1 | 1 | — | — | RSTn | 12 ↑ | SP ← SP - 2, (SP) ← PC, PC ← N x 8 | ||
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | — | RET | 10 | PC ← (SP), SP ← SP + 2 |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | addlo | addhi | CALLadd | 18 ↑ | SP ← SP - 2, (SP) ← PC, PC ← add |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | port | — | OUTport | 10 | Port ← A |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | port | — | INport | 10 | A ← Port |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | — | — | XTHL | 16 ↓ | HL ↔ (SP) |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | — | — | PCHL | 6 ↑ | PC ← HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | — | — | XCHG | 4 | HL ↔ DE |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | — | — | DI | 4 | Disable interrupts |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | — | — | SPHL | 6 ↑ | SP ← HL |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | — | — | EI | 4 | Enable interrupts |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | Clocks | Description |
| SSS DDD | 2 | 1 | 0 | CC | ALU | RP | ||||||
| B | 0 | 0 | 0 | NZ | ADD ADI (A ← A + arg) | BC | ||||||
| C | 0 | 0 | 1 | Z | ADC ACI (A ← A + arg + Cy) | DE | ||||||
| D | 0 | 1 | 0 | NC | SUB SUI (A ← A - arg) | HL | ||||||
| E | 0 | 1 | 1 | C | SBB SBI (A ← A - arg - Cy) | SP or PSW | ||||||
| H | 1 | 0 | 0 | PO | ANA ANI (A ← A ∧ arg) | |||||||
| L | 1 | 0 | 1 | PE | XRA XRI (A ← A ⊻ arg) | |||||||
| M | 1 | 1 | 0 | P | ORA ORI (A ← A ∨ arg) | |||||||
| A | 1 | 1 | 1 | N | CMP CPI (A - arg) | |||||||
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
The 8085 supports bothport-mapped and memory-mapped I/O. It supports up to 256input/output (I/O) ports via dedicated Input/Output instructions, with port addresses as operands. Port-mapped IO can be an advantage on processors with limited address space. During a port-mapped I/O bus cycle, the 8-bit I/O address is output by the CPU on both the lower and upper halves of the 16-bit address bus.
Devices designed for memory mapped I/O can also be accessed by using the LDA (load accumulator from a 16-bit address) and STA (store accumulator at a 16-bit address specified) instructions, or any other instructions that have memory operands. A memory-mapped IO transfer cycle appears on the bus as a normal memory access cycle.
Intel produced a series of development systems for the 8080 and 8085, known as the MDS-80 Microprocessor System. The original development system had an 8080 processor. Later 8085 and 8086 support was added including ICE (in-circuit emulators). It is a large and heavy desktop box, about a 20" cube (in the Intel corporate blue color) which includes a CPU, monitor, and a single 8-inch floppy disk drive. Later an external box was made available with two more floppy drives. It runs theISIS operating system and can also operate anemulator pod and an externalEPROM programmer. This unit uses the Multibus card cage which was intended just for the development system. A surprising number of spare card cages and processors were being sold, leading to the development of the Multibus as a separate product.
The later iPDS is a portable unit, about 8" × 16" × 20", with a handle. It has a small green screen, a keyboard built into the top, a 5¼ inch floppy disk drive, and runs the ISIS-II operating system. It can also accept a second 8085 processor, allowing a limited form of multi-processor operation where both processors run simultaneously and independently. The screen and keyboard can be switched between them, allowing programs to be assembled on one processor (large programs took a while) while files are edited in the other. It has abubble memory option and various programming modules, including EPROM, andIntel 8048 and8051 programming modules which are plugged into the side, replacing stand-alone device programmers. In addition to an 8080/8085 assembler, Intel produced a number of compilers including those forPL/M-80 andPascal, and a set of tools for linking and statically locating programs to enable them to be burned intoEPROMs and used inembedded systems.
A lower cost "MCS-85 System Design Kit" (SDK-85) board contains an 8085 CPU, an 8355 ROM containing a debugging monitor program, an 8155 RAM and 22 I/O ports, an 8279 hex keypad and 8-digit 7-segment LED, and a TTY (Teletype)20 mA current loop serial interface. Pads are available for one more 2K×8 8755 EPROM, and another256 byte RAM 8155 I/O Timer/Counter can be optionally added. All data, control, and address signals are available on dual pin headers, and a large prototyping area is provided.
| Model Number | Process | Clock Speed | Tempe- rature Range | Current Rating | Power Tolerance | Package | Date of Release | Price (USD) [list 1] | |
|---|---|---|---|---|---|---|---|---|---|
| Node | Tech- nology | ||||||||
| 8085A[3] | NMOS | 3 μm | 3 MHz | 170 mA | ± 5% | 6.25 | |||
| P8085AH[3] | HMOS II | 2 μm | 3 MHz | 135 mA | ± 10% | Plastic | Jul/Aug 1981 | 4.40 | |
| 8085-2[8] | 5 MHz | ||||||||
| 8085A-2[3] | NMOS | 3 μm | 5 MHz | 170 mA | ± 5% | 8.75 | |||
| P8085AH-2[3] | HMOS II | 2 μm | 5 MHz | 135 mA | ± 10% | Plastic | Jul/Aug 1981 | 5.80 | |
| P8085AH-1[3] | HMOS II | 2 μm | 6 MHz | Plastic | Jul/Aug 1981 | 12.45 | |||
| ID8085[9] | 3 MHz | Industrial | Mar/Apr 1979 | 38.75 | |||||
| M8085A[10] | 3 MHz | Military | Mar/Apr 1979 | 110.00 | |||||
The 8085 processor was used in a few early personal computers, for example, theTRS-80 Model 100 line used an OKI manufactured 80C85 (MSM80C85ARS). TheCMOS version 80C85 of the NMOS/HMOS 8085 processor has several manufacturers. IBM used the 8085 in theIBM System/23 Datamaster concealed under the reference 4178615.[11] In theSoviet Union, an 80C85 clone was developed under thedesignation IM1821VM85A (Russian:ИМ1821ВМ85А [ru]) which in[update] 2016 was still in production.[12] Some manufacturers provide variants with additional functions such as additional instructions.[citation needed]
Theradiation hardened version of the 8085 has been in on-board instrument data processors for severalNASA andESA space physics missions in the 1990s and early 2000s, includingCRRES,Polar,FAST,Cluster,HESSI, theSojourner Mars Rover,[13] andTHEMIS. The Swiss company SAIA used the 8085 and the 8085–2 as the CPUs of their PCA1 line ofprogrammable logic controllers during the 1980s.
Pro-Log Corp. put the 8085 and supporting hardware on an STD Bus format card containing CPU, RAM, sockets for ROM/EPROM, I/O and external bus interfaces. The included Instruction Set Reference Card uses entirely different mnemonics for the Intel 8085 CPU. The product was a direct competitor to Intel'sMultibus card offerings.
Western Digital's WD1003-SCS is a 1:1interleaveSCSIdisk controller that interfaces toST506-style disk drives. It is an example of an embedded 8085 application that was just beyond the capabilities of availablemicrocontrollers as its RAM requiredDMA access.[14]
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The 8085 CPU is one part of a family of chips developed by Intel for building a complete system. Many of these support chips were also used with other processors. The original IBM PC based on the Intel 8088 processor used several of these chips; the equivalent functions today are provided byVLSI chips, namely the "Southbridge" chips.
In many engineering schools the 8085 processor is used in introductory microprocessor courses. Trainer kits composed of a printed circuit board, 8085, and supporting hardware are offered by various companies. These kits usually include complete documentation allowing a student to go from soldering to assembly language programming in a single course. Also, the architecture and instruction set of the 8085 are easy for a student to understand. Shared Project versions of educational and hobby 8085-basedsingle-board computers are noted below in the External Links section of this article.
Software simulators are available for the 8085 microprocessor, which allow simulated execution of opcodes in a graphical environment.
The 8085A CPU is 100% software compatible with the Intel 8080A CPU.
Simulators:
Boards:
