Theinstruction cycle (also known as thefetch–decode–execute cycle, or simply thefetch–execute cycle) is the cycle that thecentral processing unit (CPU) follows fromboot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage.
In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before the next one is started. In most modern CPUs, the instruction cycles are instead executedconcurrently, and often inparallel, through aninstruction pipeline: the next instruction starts being processed before the previous instruction has finished, which is possible because the cycle is broken up into separate steps.[1]
Theprogram counter (PC) is a register that holds the memory address of the next instruction to be executed. After each instruction copy to thememory address register (MAR), the PC can either increment the pointer to the next sequential instruction, jump to a specified pointer, or branch conditionally to a specified pointer.[2] Also, during aCPU halt, the PC holds the instruction being executed, until an external interrupt or a reset signal is received.
The MAR is responsible for storing the address describing the location of the instruction. After a read signal is initiated, the instruction in the address from the MAR is read and placed into thememory data register (MDR), also known asMemory Buffer Register (MBR). This component overall functions as an address buffer for pointing to locations in memory.
The MDR is responsible for temporarily holding instructions read from the address in MAR. It acts as a two-way register in the instruction cycle because it can take output from memory to the CPU, or output from the CPU to memory.
Thecurrent instruction register (CIR, though sometimes referred to as the instruction register, IR) is where the instruction is temporarily held, for the CPU to decode it and produce correct control signals for the execution stage.
Thecontrol unit (CU) decodes the instruction in thecurrent instruction register (CIR). Then, the CU sends signals to other components within the CPU, such as thearithmetic logic unit (ALU), or back to memory to fetch operands, or to thefloating-point unit (FPU). The ALU performs arithmetic operations based on specificopcodes in the instruction. For example, inRISC-V architecture, funct3 and funct7 opcodes exist to distinguish whether an instruction is a logical or arithmetic operation.
Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle:[3]
In addition, on most processors,interrupts can occur. This will cause the CPU to jump to an interrupt service routine, execute that, and then return to the instruction it was meant to be executing. In some cases, the instruction can be interrupted in the middle, but there will be no effect, and the instruction will be re-executed after return from the interrupt.
The first instruction cycle begins as soon as power is applied to the system, with an initial PC value that is predefined by the system's architecture (for instance, inIntel IA-32 CPUs, the predefined PC value is0xfffffff0 whereas forARM architecture CPUs, it is0x00000000.) Typically, this address points to a set of instructions inread-only memory (ROM), which begins the process of loading (orbooting) theoperating system.[4]
The fetch stage is the same for each instruction:
The decoding process allows the processor to determine what instruction is to be performed so that the CPU can tell how many operands it needs to fetch in order to perform the instruction. The opcode fetched from the memory is decoded for the next steps and moved to the appropriate registers. The decoding is typically performed bybinary decoders in the CPU's CU.[6]
There are various ways that an architecture can specify determining the address for operands, usually called theaddressing modes.[7]
Some common ways the effective address can be found are:
The CPU sends the decoded instruction (decoded from the CU) as a set of control signals to corresponding components. Depending on the type of instruction, any of these can happen:
This is the only stage of the instruction cycle that is useful from the perspective of the end-user. Everything else is overhead required to make the execute step happen.