Instruction-level parallelism (ILP) is theparallel or simultaneous execution of a sequence ofinstructions in acomputer program. More specifically, ILP refers to the average number of instructions run per step of this parallel execution.^[2]: 5

ILP must not be confused withconcurrency. In ILP, there is a single specificthread of execution of aprocess. On the other hand, concurrency involves the assignment of multiple threads to aCPU's core in a strict alternation, or in true parallelism if there are enough CPU cores, ideally one core for each runnable thread.

There are two approaches to instruction-level parallelism:hardware andsoftware.

Hardware-level ILP works upon dynamic parallelism, whereas software-level ILP works on static parallelism. Dynamic parallelism means that the processor decides at run time which instructions to execute in parallel, whereas static parallelism means thecompiler decides which instructions to execute in parallel.^{[3][clarification needed]} ThePentium processor and laterx86 processors work on the dynamic sequence of parallel execution, but theItanium processor works on the static level parallelism.

Consider the following program:

e = a + bf = c + dm = e * f

Operation 3 depends on the results of operations 1 and 2, so it cannot be calculated until both of them are completed. However, operations 1 and 2 do not depend on any other operation, so they can be calculated simultaneously. If we assume that each operation can be completed in one unit of time, then these three instructions can be completed in a total of two units of time, giving an ILP of 3/2.

A goal ofcompiler andprocessor designers is to identify and take advantage of as much ILP as possible. Ordinary programs are typically written under a sequential execution model where instructions execute one after the other and in the order specified by the programmer. ILP allows the compiler and the processor to overlap the execution of multiple instructions or even to change the order in which instructions are executed.

How much ILP exists in programs is very application-specific. In certain fields, such as graphics andscientific computing, the amount can be very large. However, workloads such ascryptography may exhibit much less parallelism.

Micro-architectural techniques that are used to exploit ILP include:

• Instruction pipelining, where the execution of multiple instructions can be partially overlapped.
• Superscalar execution,VLIW, and the closely relatedexplicitly parallel instruction computing concepts, in which multipleexecution units are used to execute multiple instructions in parallel.
• Out-of-order execution where instructions execute in any order that does not violate data dependencies. Note that this technique is independent of both pipelining and superscalar execution. Current^[when?] implementations of out-of-order executiondynamically (i.e., while the program is executing and without any help from the compiler) extract ILP from ordinary programs. An alternative is to extract this parallelism atcompile time and somehow convey this information to the hardware. Due to the complexity of scaling the out-of-order execution technique, the industry has re-examinedinstruction sets which explicitly encode multiple independent operations per instruction.
• Register renaming, which refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations, used to enable out-of-order execution.
• Speculative execution, which allows the execution of complete instructions or parts of instructions before being certain whether this execution should take place. A commonly used form of speculative execution is control flow speculation, where instructions past a control flow instruction (e.g., a branch) are executed before the target of the control flow instruction is determined. Several other forms of speculative execution have been proposed and are in use, including speculative execution driven byvalue prediction,memory dependence prediction, andcache latency prediction.
• Branch prediction, which is used to avoid stalling for control dependencies to be resolved. Branch prediction is used with speculative execution.

ILP is exploited by both the compiler and hardware, but the compiler also provides inherent and implicit ILP in programs to hardware by compile-time optimizations. Some optimization techniques for extracting available ILP in programs includeinstruction scheduling,register allocation/renaming, and memory-access optimization.

Dataflow architectures are another class of architectures where ILP is explicitly specified; for a recent^[when?] example, see theTRIPS architecture.

In recent^[when?] years, ILP techniques have been used to provide performance improvements in spite of the growing disparity between processor operating frequencies and memory access times (early ILP designs such as theIBM System/360 Model 91 used ILP techniques to overcome the limitations imposed by a relatively small register file). Presently^[when?], a cache miss penalty to main memory costs several hundreds of CPU cycles. While in principle it is possible to use ILP to tolerate even such memory latencies, the associated resource and power dissipation costs are disproportionate. Moreover, the complexity and often the latency of the underlying hardware structures results in reduced operating frequency, further reducing any benefits. Hence, the aforementioned techniques prove inadequate to keep the CPU from stalling for the off-chip data. Instead, the industry is heading towards exploiting higher levels of parallelism that can be exploited through techniques such asmultiprocessing andmultithreading.^[4]

• Data dependency
• Memory-level parallelism (MLP)

• Aiken, Alex; Banerjee, Utpal; Kejariwal, Arun; Nicolau, Alexandru (2016-11-30).Instruction Level Parallelism. Professional Computing (1 ed.). Springer.ISBN 978-1-4899-7795-3.ISBN 1-4899-7795-3. (276 pages)

• Approaches to addressing the Memory Wall
• Wired magazine article that refers to the above paper
• https://www.scribd.com/doc/33700101/Instruction-Level-Parallelism#scribd
• http://www.hpl.hp.com/techreports/92/HPL-92-132.pdfArchived 2016-03-04 at theWayback Machine

• Instruction processing
• Parallel computing

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