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Gekko

IBMGekko processor
General information
Launched	2000
Discontinued	2007
Designed by	IBM andNintendo
Common manufacturer	IBM Microelectronics
Performance
Max.CPUclock rate	486 MHz
Physical specifications
Cores	1
Cache
L1cache	32/32 KB
L2 cache	256 KB
Architecture and classification
Application	GameCube Triforce Arcade Board
Technology node	180 nm
Microarchitecture	PowerPC G3
Instruction set	PowerPC ISA 1.10
Products, models, variants
Variant	*PowerPC 750CXe
History
Predecessor	NEC VR4300
Successor	Broadway

Gekko is a superscalar out-of-order32-bitPowerPCmicroprocessor custom-made byIBM in 2000 forNintendo to use as theCPU in theirsixth generation game console, theGameCube, and later theTriforce Arcade Board.

Gekko's role in the game system was to facilitate game scripting,artificial intelligence, physics and collision detection, custom graphics lighting effects and geometry such as smooth transformations, and moving graphics data through the system.

The project was announced in 1999 whenIBM and Nintendo agreed to a$1 billion dollar contract (IBM's largest ever single order)^[1] for a CPU running at approximately 400 MHz. IBM chose to modify their existingPowerPC 750CXe processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization was to the bus architecture,DMA, compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects and could burst compressed data directly to the GPU.^{[citation needed]}

The Gekko is considered to be the direct ancestor to theBroadway processor, also designed and manufactured byIBM, that powers theWii console.

• CustomizedPowerPC 750CXe core
• Clockrate – 486MHz
• SuperscalarOut-of-order execution
• 4 stages long two-integerALUs (IU1 and IU2) – 32 bit
• 7 stages long Floating Point Unit – 64-bit double-precisionFPU, usable as 2 × 32-bitSIMD for 1.9 single-precisionGFLOPS performance using theMultiply–accumulate operation. The SIMD is often found under the denomination "paired singles."
• Branch Prediction Unit (BPU)
• Load-Store Unit (LSU)
• System Register Unit (SRU)
• Memory Management Unit (MMU)
• Branch Target Instruction Cache (BTIC)
• SIMD Instructions – PowerPC750 + roughly 50 newSIMD instructions, geared toward3D graphics
• Front-side Bus – 64-bit enhanced60x bus toGPU/chipset at 162 MHz clock with 1.3 GB/s peak bandwidth
• On-chip Cache – 64KB 8-wayassociativeL1 cache (32/32 KB instruction/data). 256 KB on-die, 2-way associative L2 cache
• DMIPS – 1125 (dhrystone 2.1)
• 180 nm IBM six-layer, copper-wire process. 43 mm²die
• 1.8V for logic andI/O. 4.9W dissipation
• 27 × 27 mmPBGA package with 256 contacts
• 6.35 million logic transistors and 18.6 million transistors total

• Broadway (microprocessor), the processor in theWii
• MIPSR4300, the processor in theNintendo 64

• "IBM, Nintendo Announce $1 Billion Technology Agreement" (Press release).IBM. May 12, 1999. Archived fromthe original on 2006-08-21.
• A PowerPC compatible processor supporting high-performance 3-D graphics

• GameCube
• IBM microprocessors
• Nintendo chips
• PowerPC microprocessors

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