FMA4 is supported inAMD processors starting with theBulldozer architecture. FMA4 was performed in hardware before FMA3 was. Support for FMA4 has been removed sinceZen 1.[2]
FMA3 and FMA4 instructions have almost identical functionality, but are not compatible. Both containfused multiply–add (FMA) instructions forfloating-point scalar andSIMD operations, but FMA3 instructions have three operands, while FMA4 ones have four. The FMA operation has the formd = round(a ·b +c), where the round function performs arounding to allow the result to fit within the destination register if there are too many significant bits to fit within the destination.
The four-operand form (FMA4) allowsa,b,c andd to be four different registers, while the three-operand form (FMA3) requires thatd be the same register asa,b orc. The three-operand form makes the code shorter and the hardware implementation slightly simpler, while the four-operand form provides more programming flexibility.
SeeXOP instruction set for more discussion of compatibility issues between Intel and AMD.
Zen: WikiChip's testing shows FMA4 still appears to work (under the conditions of the tests) despite not being officially supported and not even reported by CPUID. This has also been confirmed by Agner Fog.[8] But other tests gave wrong results.[9] AMD Official Web Site FMA4 Support Note ZEN CPUs = AMD ThreadRipper 1900x, R7 Pro 1800, 1700, R5 Pro 1600, 1500, R3 Pro 1300, 1200, R3 2200G, R5 2400G.[10][11][12]
Intel
Intel has not released CPUs with support for FMA4.
The incompatibility between Intel's FMA3 and AMD's FMA4 is due to both companies changing plans without coordinating coding details with each other. AMD changed their plans from FMA3 to FMA4 while Intel changed their plans from FMA4 to FMA3 almost at the same time. The history can be summarized as follows:
August 2007:AMD announces theSSE5 instruction set, which includes 3-operand FMA instructions. A new coding scheme (DREX) is introduced for allowing instructions to have three operands.[13]
April 2008:Intel announces theirAVX and FMA instruction sets, including 4-operand FMA instructions. The coding of these instructions uses the newVEX coding scheme,[14] which is more flexible than AMD's DREX scheme.
December 2008: Intel changes the specification for their FMA instructions from 4-operand to 3-operand instructions. The VEX coding scheme is still used.[15]
May 2009: AMD changes the specification of their FMA instructions from the 3-operand DREX form to the 4-operand VEX form, compatible with the April 2008 Intel specification rather than the December 2008 Intel specification.[16]
October 2011: AMDBulldozer processor supports FMA4.[17]
January 2012: AMD announces FMA3 support in future processors codenamed Trinity and Vishera; they are based on thePiledriver architecture.[18]
May 2012: AMD Piledriver processor supports both FMA3 and FMA4.[17]
June 2013: IntelHaswell processor supports FMA3.[19]
February 2017: The first generation of AMDRyzen processors officially supports FMA3, but not FMA4 according to theCPUID instruction.[2] There has been confusion regarding whether FMA4 was implemented or not on this processor due to errata in the initial patch to theGNU Binutils package that has since been rectified.[20][21] One unconfirmed report of wrong results[9] led to some doubt, but Mysticial (Alexander Yee, developer of y-cruncher) debunked it:[22] FMA4 worked for bit-exact bignum calculations on his Zen 1 system for years, and the one report on Reddit never had any followup investigation to rule out mistakes in the testing software before being widely repeated. The initial Ryzen CPUs could be crashed by a particular sequence of FMA3 instructions, but updated CPU microcode fixes the problem.[23]
July 2019: AMDZen 2 and later Ryzen processors don't support FMA4 at all.[24] They continue to support FMA3. Only Zen 1 and Zen+ have unofficial FMA4 support.
^Woltmann, George (Prime95)."Intel AVX and GIMPS".mersenneforum.org. Great Internet Mersenne Prime Search (GIMPS) project. Retrieved27 July 2011.FMA3 and FMA4 are not instruction sets, they are individual instructions -- fused multiply add. They could be quite useful depending on how Intel and AMD implement them{{cite web}}: CS1 maint: numeric names: authors list (link)
