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TheF16C[1] (previously/informally known asCVT16) instruction set is anx86instruction set architecture extension which provides support for converting betweenhalf-precision and standard IEEEsingle-precision floating-point formats.
The CVT16 instruction set, announced byAMD on May 1, 2009,[2] is an extension to the 128-bitSSE core instructions in thex86 andAMD64 instruction set.
CVT16 is a revision of part of theSSE5 instruction set proposal announced on August 30, 2007, which is supplemented by theXOP andFMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible withIntel'sAVX instruction extensions, while the functionality of the instructions is unchanged.
In recent documents, the name F16C is formally used in bothIntel andAMDx86-64 architecture specifications.
There are variants that convert four floating-point values in anXMM register or 8 floating-point values in aYMM register.
The instructions are abbreviations for "vector convert packed half to packed single" and vice versa:
VCVTPH2PS xmmreg,xmmrm64 – convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register.VCVTPH2PS ymmreg,xmmrm128 – convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register.VCVTPS2PH xmmrm64,xmmreg,imm8 – convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register.VCVTPS2PH xmmrm128,ymmreg,imm8 – convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register.The 8-bit immediate argument toVCVTPS2PH selects therounding mode. Values 0–4 select nearest, down, up, truncate, and the mode set inMXCSR.RC.
Support for these instructions is indicated by bit 29 of ECX afterCPUID with EAX=1.