Incomputing,double data rate (DDR) describes acomputer bus that transfers data on both the rising and falling edges of theclock signal and hence doubles thememory bandwidth by transferring data twice per clock cycle.[1][2] This is also known asdouble pumped,dual-pumped, anddouble transition. The termtoggle mode is used in the context ofNAND flash memory.
The simplest way to design a clockedelectronic circuit is to make it perform one transfer per full cycle (rise and fall) of aclock signal. This, however, requires that the clock signal changes twice per transfer, while the data lines change at most once per transfer. When operating at a high bandwidth,signal integrity limitations constrain the clockfrequency.[citation needed] By using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate.
This technique has been used for microprocessorfront-side busses,Ultra-3 SCSI, expansion buses (AGP,PCI-X[3]), graphics memory (GDDR),main memory (bothRDRAM andDDR1 throughDDR5), and theHyperTransport bus onAMD'sAthlon 64 processors. It is more recently being used for other systems with high data transfer speed requirements – as an example, for the output ofanalog-to-digital converters (ADCs).[4]
DDR should not be confused withdual channel, in which each memory channel accesses two RAM modules simultaneously. The two technologies are independent of each other and many motherboards use both, by using DDR memory in a dual channel configuration.
An alternative to double orquad pumping is to make the linkself-clocking. This tactic was chosen byInfiniBand andPCI Express.
Describing the bandwidth of a double-pumped bus can be confusing. Each clock edge is referred to as abeat, with two beats (oneupbeat and onedownbeat) per cycle. Technically, thehertz is a unit ofcycles per second, but many people refer to the number oftransfers per second. Careful usage generally talks about "500 MHz, double data rate" or "1000 MT/s", but many refer casually to a "1000 MHz bus," even though no signal cycles faster than 500 MHz.
DDR SDRAM popularized the technique of referring to the bus bandwidth inmegabytes per second, the product of the transfer rate and the bus width in bytes. DDR SDRAM operating with a 100 MHz clock is called DDR-200 (after its 200 MT/s data transfer rate), and a 64-bit (8-byte) wideDIMM operated at that data rate is called PC-1600, after its 1600 MB/s peak (theoretical) bandwidth. Likewise, 12.8 GB/s transfer rate DDR3-1600 is called PC3-12800.
Some examples of popular designations of DDR modules:
| Names | Memory clock | I/O bus clock | Transfer rate | Theoretical bandwidth |
|---|---|---|---|---|
| DDR-200, PC-1600 | 100 MHz | 100 MHz | 200 MT/s | 1.6 GB/s |
| DDR-400, PC-3200 | 200 MHz | 200 MHz | 400 MT/s | 3.2 GB/s |
| DDR2-800, PC2-6400 | 200 MHz | 400 MHz | 800 MT/s | 6.4 GB/s |
| DDR3-1600, PC3-12800 | 200 MHz | 800 MHz | 1600 MT/s | 12.8 GB/s |
| DDR4-2400, PC4-19200 | 300 MHz | 1200 MHz | 2400 MT/s | 19.2 GB/s |
| DDR4-3200, PC4-25600 | 400 MHz | 1600 MHz | 3200 MT/s | 25.6 GB/s |
| DDR5-4800, PC5-38400 | 300 MHz | 2400 MHz | 4800 MT/s | 38.4 GB/s |
| DDR5-6400, PC5-51200 | 400 MHz | 3200 MHz | 6400 MT/s | 51.2 GB/s |
DDR SDRAM uses double-data-rate signaling only on the data lines. Address and control signals are still sent to the DRAM once per clockcycle (to be precise, on the rising edge of the clock), and timing parameters such asCAS latency are specified in clock cycles. Some less common DRAM interfaces, notablyLPDDR2,GDDR5 andXDR DRAM, send commands and addresses using double data rate.DDR5 uses two 7-bit double data rate command/address buses to each DIMM, where aregistered clock driver chip converts to a 14-bit SDR bus to each memory chip.