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| Semiconductor device fabrication |
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| MOSFET scaling (process nodes) |
The termdie shrink (sometimesoptical shrink orprocess shrink) refers to thescaling ofmetal–oxide–semiconductor (MOS) devices. The act of shrinking adie creates a somewhat identical circuit using a more advancedfabrication process, usually involving an advance oflithographicnodes. This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs while at the same time allowing more processor dies to be manufactured on the same piece ofsilicon wafer, resulting in less cost per product sold.
Die shrinks are the key to lower prices and higher performance atsemiconductor companies such asSamsung,Intel,TSMC, andSK Hynix, andfabless manufacturers such asAMD (including the formerATI),NVIDIA andMediaTek.
Examples in the 2000s include the downscaling of thePlayStation 2'sEmotion Engine processor fromSony andToshiba (from180 nmCMOS in 2000 to90 nm CMOS in 2003),[1] the codenamedCedar MillPentium 4 processors (from 90 nm CMOS to65 nm CMOS) andPenryn Core 2 processors (from 65 nm CMOS to45 nm CMOS), the codenamedBrisbaneAthlon 64 X2 processors (from90 nmSOI to65 nmSOI), various generations ofGPUs from both ATI and NVIDIA, and various generations ofRAM andflash memory chips from Samsung, Toshiba and SK Hynix. In January 2010, Intel releasedClarkdaleCore i5 andCore i7 processors fabricated with a32 nm process, down from a previous45 nm process used in older iterations of theNehalemprocessormicroarchitecture. Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through itsTick–Tock model. In thisbusiness model, every newmicroarchitecture (tock) is followed by a die shrink (tick) to improve performance with the same microarchitecture.[2]
Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off insemiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increasedclock rate headroom, and lower prices.[2] Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.
In CPU fabrications, a die shrink always involves an advance to alithographic node as defined byITRS (see list). For GPU andSoC manufacturing, the die shrink often involves shrinking the die on a node not defined by the ITRS, for instance, the 150 nm, 110 nm, 80 nm, 55 nm, 40 nm and more currently 8 nm nodes, sometimes referred to as "half-nodes". This is a stopgap between two ITRS-definedlithographic nodes (thus called a "half-node shrink") before further shrink to the lower ITRS-defined nodes occurs, which helps save additional R&D cost. The choice to perform die shrinks to either full nodes or half-nodes rests with the foundry and not the integrated circuit designer.
| Main ITRS node | Stopgap half-node |
|---|---|
| 250 nm | 220 nm |
| 180 nm | 150 nm |
| 130 nm | 110 nm |
| 90 nm | 80 nm |
| 65 nm | 55 nm |
| 45 nm | 40 nm |
| 32 nm | 28 nm |
| 22 nm | 20 nm |
| 14 nm | 12 nm[3] |
| 10 nm | 8 nm |
| 7 nm | 6 nm |
| 5 nm | 4 nm |
| 3 nm | — |
