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ADIMM (Dual In-line Memory Module) is a popular type ofmemory module used in computers. It is aprinted circuit board with one or both sides (front and back) holdingDRAMchips andpins.[1] The vast majority of DIMMs are manufactured in compliance withJEDEC memory standards, although there are proprietary DIMMs. DIMMs come in a variety of speeds and capacities, and are generally one of two lengths: PC, which are 133.35 mm (5.25 in), and laptop (SO-DIMM), which are about half the length at 67.60 mm (2.66 in).[2]
DIMMs (Dual In-line Memory Module) were a 1990s upgrade forSIMMs (Single In-line Memory Modules)[3][4] asIntelP5-basedPentium processors began to gain market share. The Pentium had a 64-bitbus width, which would require SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel.
DIMMs were introduced to eliminate this disadvantage. The contacts on SIMMs on both sides are redundant, while DIMMs have separate electrical contacts on each side of the module.[5] This allowed them to double the SIMMs 32-bit data path into a 64-bit data path.[6]
The name "DIMM" was chosen as an acronym forDual In-line Memory Module symbolizing the split in the contacts of a SIMM into two independent rows.[6] Many enhancements have occurred to the modules in the intervening years, but the word "DIMM" has remained as one of the generic terms[clarification needed] for a computer memory module.
DIMMs come in a number of board sizes. In order of descending size: DIMM, SO-DIMM, MiniDIMM, and MicroDIMM.
Regular DIMMs are generally 133.35 mm in length, while SO-DIMMs are generally 67.6 mm in length.[2]
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ASO-DIMM (pronounced "so dim"/ˈsoʊdɪm/, also spelledSODIMM) orsmall outline DIMM, is a smaller alternative to a DIMM, being roughly half the physical size of a regular DIMM. The first SO-DIMMs had 72 pins and were introduced by JEDEC in 1997.[7][8][9] Before its introduction, many laptops would use proprietary[10] RAM modules which were expensive and hard to find.[7][11]
SO-DIMMs are often used in computers that have limited space, which includelaptops,notebook computers, small-footprint personal computers such as those based onNano-ITX motherboards, high-end upgradable officeprinters, andnetworking hardware such asrouters andNAS devices.[12] They are usually available with the same size data path and speed ratings of the regular DIMMs though normally with smaller capacities.
Different generations of memory are not interchangable: neitherforward compatible norbackward compatible. To make this difference clear and avoid any confusion, their DIMM modules all have different pin counts and/or different notch positions. DDR5 SDRAM is the most recent type of DDR memory and has been in use since 2020.
Besides pin count there are also physical notches to differentiate the incompatible types of DIMM. For example, the ancient 168-pin SDR SDRAM had different voltage ratings (5.0 V or 3.3 V) and a difference ofregistered (buffered) vsunbuffered. As a result it has two notch positions to prevent the insertion of the wrong type of module.
Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in 1.5 inches (38 mm) and 1.7 inches (43 mm) heights, with the nominal value being 30 millimetres (1.2 in). When1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75 inches (44 mm) high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" (LP) height of around 1.2 inches (30 mm). These fit into vertical DIMM sockets for a 1U platform.
With the advent ofblade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around 18 millimetres (0.71 in). These will fit vertically inATCA systems.
Very similar height levels are used for SO-DIMM, Mini-DIMM and Micro-DIMM.[15]
| Generation | Full-height (1U) | Very low profile (VLP) | Notes | ||
|---|---|---|---|---|---|
| Nominal | Maximum | Nominal | Maximum | ||
| DDR2[17] | 30.00 millimetres (1.181 in) | 30.50 millimetres (1.201 in) | — | — | |
| DDR3[18] | 30.00 millimetres (1.181 in) | 30.50 millimetres (1.201 in) | 18.75 millimetres (0.738 in) | 18.90 millimetres (0.744 in) | |
| DDR4[19] | 31.25 millimetres (1.230 in) | 31.40 millimetres (1.236 in) | 18.75 millimetres (0.738 in) | 18.90 millimetres (0.744 in) | |
| DDR5[20] | 31.25 millimetres (1.230 in) | 31.40 millimetres (1.236 in) | — | — |
|
Notes:
As of Q2 2017, Asus has had aPCIe based "DIMM.2", which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to twoM.2NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support from other than Asus.[21]
Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with up to nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits. High-capacity DIMMs such as 256 GB DIMMs can have up to 19 chips per side.
In the case of "×4" registered DIMMs, the data width per side is 36 bits; therefore, thememory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. For "×8" registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).
The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted.
Sometimes, memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called arank. Of the ranks that share the same memory slot, i.e. on the same module, only one rank may be accessed at any given time. The rank to be accessed is specified by activating its chip select (CS) signal, while the other ranks on the same module are deactivated for the duration of the operation by having their corresponding CS signals deactivated.
After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. These amplifiers typically have 3 cycles of idle time for recharging between accesses. By interleaving the memory (e.g. cells 0, 4, 8, ... are stored in one rank, cells 1, 5, 9, ... in another rank, and so on), sequential memory accesses can be performed more rapidly by alternating which rank is active, thus overlapping the active memory access with recharge time for the inactive ranks.
As of 2025[update], DIMMs are commonly manufactured with one, two, or four ranks per module. Consumer DIMM vendors have began to distinguish between single- and dual-ranked DIMMs since around 2020.
DIMMs are often referred to as "single-sided" or "double-sided" to describe whether the DRAM chips are located on one or both sides of the module'sprinted circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed. Indeed, quad-ranked DIMMs exist.
JEDEC decided that the terms "dual-sided", "double-sided", or "dual-banked" were not correct when applied toregistered DIMMs (RDIMMs).
Multiplexed Rank DIMM (MRDIMM) allow data from multiple ranks to be transmitted on the same channel. It was announced for DDR5 in July 2024 and is expected to be backwards compatible with DDR5 RDIMM.[22]
A DIMM's capacity and other operational parameters may be identified withserial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPDEEPROM connects to theSystem Management Bus and may also contain thermal sensors (TS-on-DIMM).[23]
For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.
DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based onDouble Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.
Another influence is Column Access Strobe (CAS) latency, or CL, which affects memory access speed. This is the delay time between the READ command and the moment data is available. See main articleCAS/CL andmemory timing.
| Chip | Module | Effective clock (MHz) | Transfer rate (MT/s) | Voltage (V) |
|---|---|---|---|---|
| SDR-66 | PC-66 | 66 | 66 | 3.3 |
| SDR-100 | PC-100 | 100 | 100 | 3.3 |
| SDR-133 | PC-133 | 133 | 133 | 3.3 |
| Chip | Module | Memory clock (MHz) | I/O bus clock (MHz) | Transfer rate (MT/s) | Voltage (V) |
|---|---|---|---|---|---|
| DDR-200 | PC-1600 | 100 | 100 | 200 | 2.5 |
| DDR-266 | PC-2100 | 133 | 133 | 266 | 2.5 |
| DDR-333 | PC-2700 | 166 | 166 | 333 | 2.5 |
| DDR-400 | PC-3200 | 200 | 200 | 400 | 2.6 |
| Chip | Module | Memory clock (MHz) | I/O bus clock (MHz) | Transfer rate (MT/s) | Voltage (V) |
|---|---|---|---|---|---|
| DDR2-400 | PC2-3200 | 100 | 200 | 400 | 1.8 |
| DDR2-533 | PC2-4200 | 133 | 266 | 533 | 1.8 |
| DDR2-667 | PC2-5300 | 166 | 333 | 667 | 1.8 |
| DDR2-800 | PC2-6400 | 200 | 400 | 800 | 1.8 |
| DDR2-1066 | PC2-8500 | 266 | 533 | 1066 | 1.8 |
| Chip | Module | Memory clock (MHz) | I/O bus clock (MHz) | Transfer rate (MT/s) | Voltage (V) |
|---|---|---|---|---|---|
| DDR3-800 | PC3-6400 | 100 | 400 | 800 | 1.5 |
| DDR3-1066 | PC3-8500 | 133 | 533 | 1066 | 1.5 |
| DDR3-1333 | PC3-10600 | 166 | 667 | 1333 | 1.5 |
| DDR3-1600 | PC3-12800 | 200 | 800 | 1600 | 1.5 |
| DDR3-1866 | PC3-14900 | 233 | 933 | 1866 | 1.5 |
| DDR3-2133 | PC3-17000 | 266 | 1066 | 2133 | 1.5 |
| DDR3-2400 | PC3-19200 | 300 | 1200 | 2400 | 1.5 |
| Chip | Module | Memory clock (MHz) | I/O bus clock (MHz) | Transfer rate (MT/s) | Voltage (V) |
|---|---|---|---|---|---|
| DDR4-1600 | PC4-12800 | 200 | 800 | 1600 | 1.2 |
| DDR4-1866 | PC4-14900 | 233 | 933 | 1866 | 1.2 |
| DDR4-2133 | PC4-17000 | 266 | 1066 | 2133 | 1.2 |
| DDR4-2400 | PC4-19200 | 300 | 1200 | 2400 | 1.2 |
| DDR4-2666 | PC4-21300 | 333 | 1333 | 2666 | 1.2 |
| DDR4-3200 | PC4-25600 | 400 | 1600 | 3200 | 1.2 |
| Chip | Module | Memory clock (MHz) | I/O bus clock (MHz) | Transfer rate (MT/s) | Voltage (V) |
|---|---|---|---|---|---|
| DDR5-4000 | PC5-32000 | 2000 | 2000 | 4000 | 1.1 |
| DDR5-4400 | PC5-35200 | 2200 | 2200 | 4400 | 1.1 |
| DDR5-4800 | PC5-38400 | 2400 | 2400 | 4800 | 1.1 |
| DDR5-5200 | PC5-41600 | 2600 | 2600 | 5200 | 1.1 |
| DDR5-5600 | PC5-44800 | 2800 | 2800 | 5600 | 1.1 |
| DDR5-6000 | PC5-48000 | 3000 | 3000 | 6000 | 1.1 |
| DDR5-6200 | PC5-49600 | 3100 | 3100 | 6200 | 1.1 |
| DDR5-6400 | PC5-51200 | 3200 | 3200 | 6400 | 1.1 |
| DDR5-6800 | PC5-54400 | 3400 | 3400 | 6800 | 1.1 |
| DDR5-7200 | PC5-57600 | 3600 | 3600 | 7200 | 1.1 |
| DDR5-7600 | PC5-60800 | 3800 | 3800 | 7600 | 1.1 |
| DDR5-8000 | PC5-64000 | 4000 | 4000 | 8000 | 1.1 |
| DDR5-8400 | PC5-67200 | 4200 | 4200 | 8400 | 1.1 |
| DDR5-8800 | PC5-70400 | 4400 | 4400 | 8800 | 1.1 |
ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips as a result.
It is electrically demanding for a memory controller to drive many DIMMs.Registered DIMMs add ahardware register to the clock, address, and command lines so that the signals are refreshed on the DIMM, allowing a reduced load on the memory controller. Variants include LRDIMM with all lines buffered and CUDIMM/CSODIMM with only the clock signal buffered. The register feature often occurs with ECC, but they do not actually depend on each other and can occur independently.
In the case of SIMM, the connectors are only present on the single side of the module...DIMM has a row of connectors on both sides(front and back) of the module
