Current mode logic (CML), orsource-coupled logic (SCL), is a digital design style used both forlogic gates and forboard-level digital signaling of digital data.
The basic principle of CML is thatcurrent from aconstant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented. Typically, the generator is connected to the two sources of a pair of differentialFETs, with the two paths being their two drains. Thebipolar equivalentemitter-coupled logic (ECL) operates in a contrasting fashion, still differential but with the output being taken from the emitters of the BJT transistors (rather than the collectors, which would be analogous to the drains of the FETs).
As adifferentialPCB-level interconnect, it is intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standardprinted circuit boards.[1]
The transmission is point-to-point, unidirectional, and is usuallyterminated at the destination with 50Ωresistors toVcc on both differential lines. CML is frequently used in interfaces to fiber optic components. The difference of principal between CML andECL as a link technology is theoutput impedance of the driver stage: theemitter follower of ECL has a low resistance of around 5 Ω whereas CML connects to the drains of the driving transistors, that have a high impedance, and so theimpedance of thepull up/down network (typically 50 Ω resistive) is the effective output impedance.Matching this drive impedance close to the driventransmission line'scharacteristic impedance greatly reduces undesirable ringing.
CML signals have also been found useful for connections between modules. CML is thephysical layer used inDVI,HDMI andFPD-Link III video links, the interfaces between adisplay controller and amonitor.[2]
In addition, CML has been widely used in high-speed integrated systems, such as forserial datatransceivers andfrequency synthesizers intelecommunication systems.
The fast operation of CML circuits is mainly due to their lower output voltage swing compared to the staticCMOS circuits, as well as the very fast current switching taking place at the input differential pair transistors. One of the primary requirements of a current-mode logic circuit is that the current bias transistor must remain in the saturation region to maintain a constant current.
Recently, CML has been used in ultra-low power applications. Studies show that while the leakage current in conventional static CMOS circuits is becoming a major challenge in lowering the energy dissipation, good control of CML current consumption makes them a very good candidate for extremely low power use. Called subthreshold CML or subthreshold source coupled logic (STSCL),[3][4][5] the current consumption of each gate can be reduced down to a few tens of picoamps.