Achip scale package orchip-scale package (CSP) is a type ofintegrated circuit package.[1]
Originally, CSP was the acronym forchip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted tochip-scale packaging. According toIPC's standard J-STD-012,Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of thedie and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.
The concept was first proposed by Junichi Kasai ofFujitsu and Gen Murakami ofHitachi Cable in 1993. The first concept demonstration however came fromMitsubishi Electric.[2]
The die may be mounted on aninterposer upon which pads or balls are formed, like withflip chipball grid array (BGA) packaging, or the pads may be etched or printed directly onto thesilicon wafer, resulting in a package very close to the size of the silicon die: such a package is called awafer-level package (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such asAdvanced Semiconductor Engineering (ASE).[3][4]
Chip scale packages can be classified into the following groups:
