32 ×128-bit registers[1] for scalar 32- and 64-bitFP orSIMD FP or integer; or cryptography
AArch64 orARM64 is the64-bit Execution state of theARM architecture family. It was first introduced with theArmv8-A architecture, and has had many extension updates.[2]
AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
A new exception system:
Fewer banked registers and modes.
Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.
Extension: Data gathering hint (ARMv8.0-DGH).
AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A, and in all versions of ARMv9-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M.
Announced in October 2011,[4]ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit Execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit Execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit Arm) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provideuser-space compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bithypervisor.[1] ARM announced theirCortex-A53 andCortex-A57 cores on 30 October 2012.[5]Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S).AppliedMicro, using anFPGA, was the first to demo ARMv8-A.[6] The first ARMv8-ASoC fromSamsung is the Exynos 5433 used in theGalaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in abig.LITTLE configuration; but it will run only in AArch32 mode.[7]ARMv8-A includes the VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supportingAES,SHA-1/SHA-256 andfinite field arithmetic.[8]
An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.[9] For example, the ARM Cortex-A32 supports only AArch32,[10] theARM Cortex-A34 supports only AArch64,[11] and theARM Cortex-A72 supports both AArch64 and AArch32.[12] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.[9]
In December 2014, ARMv8.1-A,[13] an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.
Instruction set enhancements included the following:
A set of AArch64 atomic read-write instructions.
Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations:
Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.
Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.
The instructions are added in vector and scalar forms.
A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.
The optional CRC instructions in v8.0 become a requirement in ARMv8.1.
Enhancements for the exception model and memory translation system included the following:
A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.
An increased VMID range for virtualization; supports a larger number of virtual machines.
Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.
A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.
The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization ofhigh-performance computing scientific workloads.[16][17] The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is complementary to, and does not replace, theNEON extensions.
A 512-bit SVE variant has already been implemented on theFugaku supercomputer using theFujitsu A64FX ARM processor; this computer[18] was the fastest supercomputer in the world for two years, from June 2020[19] to May 2022.[20] A more flexible version, 2x256 SVE, was implemented by theAWS Graviton3 ARM processor.
SVE is supported by theGCC compiler, with GCC 8 supporting automatic vectorization[17] and GCC 10 supporting C intrinsics. As of July 2020[update],LLVM andclang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.[21]
In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:[22]
Pointer authentication (PAC)[23][24] (AArch64 only); mandatory extension (based on a new block cipher,QARMA[25]) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips).
Nested virtualization (AArch64 only).
Advanced SIMDcomplex number support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees.
New FJCVTZS (Floating-pointJavaScript Convert to Signed fixed-point, rounding toward Zero) instruction.[26]
A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model ofC++11/C11 (the default C++11/C11 consistency model was already supported in previous ARMv8).
ID mechanism support for larger system-visible caches (AArch64 and AArch32).
ARMv8.3-A architecture is now supported by (at least) theGCC 7 compiler.[27]
Branch Target Indicators (BTI) (AArch64) to reduce "the ability of an attacker to execute arbitrary code". Like pointer authentication, the relevant instructions are no-ops on earlier versions of ARMv8-A.
Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards".
On 2 August 2019,Google announcedAndroid would adopt Memory Tagging Extension (MTE).[35]
In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all the features from ARMv8.5.[36][37][38] ARMv9-A also adds:
Scalable Vector Extension 2 (SVE2). SVE2 builds on SVE's scalable vectorization for increased fine-grainData Level Parallelism (DLP), to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently useNeon.[39] TheLLVM/Clang 9.0 andGCC 10.0 development codes were updated to support SVE2.[39][40]
SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT.
Enhancements for virtualization, system management and security.
And the following extensions (thatLLVM 11 already added support for[44]):
Enhanced Counter Virtualization (ARMv8.6-ECV).
Fine-Grained Traps (ARMv8.6-FGT).
Activity Monitors virtualization (ARMv8.6-AMU).
For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use.[45]
In October 2023, ARMv9.5-A was announced, including:[51]
FP8 support (E5M2 and E4M3 formats) added to:
SME2
SVE2
Advanced SIMD (Neon)
Live migration of Virtual Machines using Hardware Dirty state tracking structures (FEAT_HDBSS)
Checked Point Arithmetic
Support for using a combination of the PC and SP as the modifier when generating or checking Pointer Authentication codes.
Support for Realm Management Extension (RME) enabled designs, support for non-secure only in the Granule Protection Tables and the ability to disable certain Physical Address Spaces (PAS).
EL3 configuration write-traps.
Breakpoint support for address range and mismatch triggering without the need for linking.
Support for efficiently delegating SErrors from EL3 to EL2 or EL1.
This sectionneeds expansion with: examples and additional citations. You can help byadding to it. Relevant discussion may be found onTalk:AArch64.(May 2021)
TheARM-R architecture, specifically the Armv8-R profile, is designed to address the needs of real-time applications, where predictable and deterministic behavior is essential. This profile focuses on delivering high performance, reliability, and efficiency in embedded systems where real-time constraints are critical.
With the introduction of optional AArch64 support in the Armv8-R profile, the real-time capabilities have been further enhanced. The Cortex-R82[53] is the first processor to implement this extended support, bringing several new features and improvements to the real-time domain.[54]
The A64 instruction[26] set in the Cortex-R82 provides 64-bit data handling and operations, which improves performance for certain computational tasks and enhances overall system efficiency.[53]
Example Instruction:ADD X0, X1, X2 adds the values in 64-bit registers X1 and X2 and stores the result in X0. This 64-bit operation allows for larger and more complex calculations compared to the 32-bit operations of the previous A32 instruction set.
Enhanced Memory Management:
Memory Barrier Instructions: The Cortex-R82 introduces improved memory barrier instructions to ensure proper ordering of memory operations, which is critical in real-time systems where the timing of memory operations must be strictly controlled.[55]
Data Synchronization Barrier (DSB): Ensures that all data accesses before the barrier are completed before continuing with subsequent operations.
Data Memory Barrier (DMB): Guarantees that all memory accesses before the barrier are completed before any memory accesses after the barrier can proceed.
Example: In a real-time automotive control system, DSB might be used to ensure that sensor data is fully written to memory before the system proceeds with processing or decision-making, preventing data corruption or inconsistencies.
Improved Address Space:
64-bit Addressing: AArch64 allows the Cortex-R82 to address a much larger memory space compared to its 32-bit predecessors, making it suitable for applications requiring extensive memory.
Example: A complex industrial automation system can utilize the expanded address space to manage large data sets and buffers more efficiently, improving system performance and capability.
Real-Time Performance Enhancements:
Interrupt Handling: With AArch64 support, the Cortex-R82 can handle interrupts with lower latency and improved predictability, crucial for real-time operations.
Example: In a robotics application, the Cortex-R82's enhanced interrupt handling can ensure timely responses to external stimuli, such as changes in sensor data or control commands.
^"GCC 7 Release Series – Changes, New Features, and Fixes".The ARMv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option. [..] The option -msign-return-address= is supported to enable return address protection using ARMv8.3-A Pointer Authentication Extensions.
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