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Incomputer architecture,256-bitintegers,memory addresses, or otherdata units are those that are 256bits (32octets) wide. Also, 256-bitcentral processing unit (CPU) andarithmetic logic unit (ALU) architectures are those that are based onregisters,address buses, ordata buses of that size.There are currently no mainstream general-purposeprocessors built to operate on 256-bit integers or addresses, though a number of processors do operate on 256-bit data.
A 256-bit quantity can store 2256 different values. The range ofinteger values that can be stored in 256 bits depends on theinteger representation used.
The range of a signed 256-bit integer is from −57,896,044,618,658,097,711,785,492,504,343,953,926,634,992,332,820,282,019,728,792,003,956,564,819,968 to 57,896,044,618,658,097,711,785,492,504,343,953,926,634,992,332,820,282,019,728,792,003,956,564,819,967.
256-bit processors could be used for addressing directly up to 2256 bytes. Already 2128 (for128-bit addressing) would greatly exceed the total data stored on Earth as of 2018, which has been estimated to be around 33.3ZBs (over 274 bytes).[1]
Xbox 360 was the first high-definition gaming console to utilize theATI Technologies 256-bit GPUXenos[2] before the introduction of the current gaming consoles especiallyNintendo Switch.
Some buses on the newerSystem on a chip (e.g.Tegra developed byNvidia) utilize 64-bit, 128-bit, 256-bit, or higher.
CPUs featureSIMD instruction sets (Advanced Vector Extensions and theFMA instruction set etc.) where 256-bit vectorregisters are used to store several smaller numbers, such as eight 32-bitfloating-point numbers, and a singleinstruction can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only theirregisters have the size of 256-bits. Binary digits are found together in128-bit collections.
ModernGPU chips may operate data across a 256-bit memory bus (or possibly a512-bit bus withHBM3[3]).
TheEfficeon processor wasTransmeta's second-generation 256-bitVLIW design which employed a software engine to convert code written forx86 processors to the native instruction set of the chip.[4][5]
TheDARPA funded Data-Intensive Architecture (DIVA) system incorporatedprocessor-in-memory (PIM) 5-stagepipelined 256-bit datapath, complete with register file and ALU blocks in a "WideWord" processor in 2002.[6]