Semiconductor device fabrication
MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977  1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2025 001 nm ~ 2027
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
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The"14 nanometer process" refers to a marketing term for theMOSFETtechnology node that is the successor to the"22 nm" (or "20 nm") node. The "14 nm" was so named by theInternational Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following "22 nm" was expected to be "16 nm". All "14 nm" nodes useFinFET (fin field-effect transistor) technology, a type ofmulti-gate MOSFET technology that is a non-planar evolution of planarsiliconCMOS technology.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;^[1] neither gate length, metal pitch or gate pitch on a "14nm" device is fourteen nanometers.^[2][3][4] For example, TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes intransistor density, and TSMC's "7 nm" processes are dimensionally similar to Intel's "10 nm" process.^[5]

Samsung Electronics taped out a "14 nm" chip in 2014, before manufacturing"10 nm class" NAND flash chips in 2013.^{[dubious –discuss][clarification needed]} The same year,SK Hynix began mass-production of "16 nm"NAND flash, andTSMC began "16 nm" FinFET production. The following year,Intel began shipping "14 nm" scale devices to consumers.^{[needs update]}

The resolutions of a "14 nm" device are difficult to achieve in a polymericresist, even withelectron beam lithography. In addition, the chemical effects ofionizing radiation also limit reliable resolution to about30 nm, which is also achievable using current state-of-the-artimmersion lithography.Hardmask materials andmultiple patterning are required.

A more significant limitation comes from plasma damage tolow-k materials. The extent of damage is typically 20 nm thick,^[6] but can also go up to about 100 nm.^[7] The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrainedsilicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantialleakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the "16 nm"/"14 nm" node circa 2010.^[8]Samsung andSynopsys had also, at that time, begun implementing double patterning in "22 nm" and "16 nm" design flows.^[9]Mentor Graphics reported taping out "16 nm" test chips in 2010.^{[10][needs update]} On January 17, 2011,IBM announced that they were teaming up withARM to develop "14 nm" chip processing technology.^{[11][needs update]}

On February 18, 2011,Intel announced that it would construct a new $5 billionsemiconductor fabrication plant inArizona, designed to manufacture chips using the "14 nm" manufacturing processes and leading-edge 300 mmwafers.^[12][13] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.^{[14][needs update]} On May 17, 2011, Intel announced a roadmap for 2014 that included "14 nm" transistors for theirXeon,Core, andAtom product lines.^{[15][needs update]}

In the late 1990s, Hisamoto's Japanese team fromHitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, includingTSMC'sChenming Hu and variousUC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17 nm process. They later developed a 15 nm FinFET process in 2001.^[16] In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian),Jeffrey Bokor, David Kyser,Chenming Hu (Taiwan Semiconductor Manufacturing Company), andTsu-Jae King Liu, demonstratedFinFET devices down to10 nm gate length.^[16][17]

In 2005,Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nmfin width, using a sidewall spacer process.^[18] It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.^{[19][needs update]} In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.^[20]

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a "16 nm"SRAM chip.^{[21][needs update]}

In September 2011,Hynix announced the development of "15 nm" NAND cells.^{[22][needs update]}

In December 2012,Samsung Electronics taped out a "14 nm" chip.^{[23][needs update]}

In September 2013,Intel demonstrated anUltrabook laptop that used a "14 nm"Broadwell CPU, and Intel CEOBrian Krzanich said, "[CPU] will be shipping by the end of this year."^[24] However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.^{[25][needs update]}

In August 2014, Intel announced details of the "14 nm" microarchitecture for its upcomingCore M processors, the first product to be manufactured on Intel's "14 nm" manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generationtri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.^{[26][needs update]}

In 2018 a shortage of "14 nm" fab capacity was announced by Intel.^{[27][needs update]}

In 2013,SK Hynix began mass-production of "16 nm"NAND flash,^[28]TSMC began "16 nm"FinFET production,^[29] andSamsung began "10 nm class" NAND flash production.^[30]

On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to thelow-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.^{[31][needs update]}

In February 2015, Samsung announced that their flagship smartphones, theGalaxy S6 and S6 Edge, would feature "14 nm"Exynossystems on chip (SoCs).^{[32][needs update]}

On March 9, 2015,Apple Inc. released the "Early 2015"MacBook andMacBook Pro, which utilized "14 nm" Intel processors. Of note is the i7-5557U, which hasIntel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.^{[33][34][needs update]}

On September 25, 2015, Apple Inc. released theiPhone 6S & 6S Plus, which were erstwhile equipped with "desktop-class"A9 chips^[35] that are fabricated in both "14 nm" by Samsung and "16 nm" byTSMC (Taiwan Semiconductor Manufacturing Company).^{[needs update]}

In May 2016,Nvidia released itsGeForce 10 seriesGPUs based on thePascal architecture, which incorporates TSMC's "16 nm"FinFET technology and Samsung's "14 nm" FinFET technology.^{[36][37][needs update]}

In June 2016,AMD released itsRadeon RX 400 GPUs based on thePolaris architecture, which incorporated "14 nm" FinFET technology from Samsung. The technology had at that time been licensed toGlobalFoundries for dual sourcing.^{[38][needs update]}

On August 2, 2016,Microsoft released theXbox One S, which utilized "16 nm" by TSMC.^{[needs update]}

On March 2, 2017, AMD released itsRyzen CPUs based on theZen architecture, incorporating "14 nm" FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.^{[39][needs update]}

TheNEC SX-Aurora TSUBASA processor, introduced in October 2017,^[40] used a "16 nm" FinFET process from TSMC and was designed for use withNEC SX supercomputers.^{[41][needs update]}

On July 22, 2018, GlobalFoundries announced their "12 nm" Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.^{[42][needs update]}

In September 2018, Nvidia released GPUs based on theirTuring (microarchitecture), which were made on TSMC's "12 nm" process and had a transistor density of 24.67 million transistors per square millimeter.^{[43][needs update]}

Lower numbers are better, except for transistor density, in which case the opposite is true.^[65] Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).^{[66][67][68][69][70]}

^[71]

• International Technology Roadmap for Semiconductors lithography nodes

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