Tiled rendering is the process of subdividing acomputer graphics image by a regulargrid inoptical space and rendering each section of the grid, ortile, separately. The advantage to this design is that the amount of memory and bandwidth is reduced compared toimmediate mode rendering systems that draw the entire frame at once. This has made tile rendering systems particularly common for low-powerhandheld device use. Tiled rendering is sometimes known as a "sort middle" architecture, because it performs the sorting of the geometry in the middle of thegraphics pipeline instead of near the end.[1]
Creating a 3D image for display consists of a series of steps. First, the objects to be displayed are loaded into memory from individualmodels. The system then applies mathematical functions to transform the models into a common coordinate system, theworld view. From this world view, a series of polygons (typically triangles) is created that approximates the original models as seen from a particular viewpoint, thecamera. Next, a compositing system produces an image by rendering the triangles and applyingtextures to the outside. Textures are small images that are painted onto the triangles to produce realism. The resulting image is then combined with various special effects, and moved into aframe buffer, which video hardware then scans to produce the displayed image. This basic conceptual layout is known as thedisplay pipeline.
Each of these steps increases the amount of memory needed to hold the resulting image. By the time it reaches the end of the pipeline the images are so large that typicalgraphics card designs often use specialized high-speed memory and a very fastcomputer bus to provide the required bandwidth to move the image in and out of the various sub-components of the pipeline. This sort of support is possible on dedicated graphics cards, but as power and size budgets become more limited, providing enough bandwidth becomes expensive in design terms.
Tiled renderers address this concern by breaking down the image into sections known as tiles, and rendering each one separately. This reduces the amount of memory needed during the intermediate steps, and the amount of data being moved about at any given time. To do this, the system sorts the triangles making up the geometry by location, allowing to quickly find which triangles overlap the tile boundaries. It then loads just those triangles into the rendering pipeline, performs the various rendering operations in theGPU, and sends the result to theframe buffer. Very small tiles can be used, 16×16 and 32×32 pixels are popular tile sizes, which makes the amount of memory and bandwidth required in the internal stages small as well. And because each tile is independent, it naturally lends itself to simple parallelization.
In a typical tiled renderer, geometry must first be transformed into screen space and assigned to screen-space tiles. This requires some storage for the lists of geometry for each tile. In early tiled systems, this was performed by theCPU, but all modern hardware contains hardware to accelerate this step. The list of geometry can also be sorted front to back, allowing the GPU to usehidden surface removal to avoid processing pixels that are hidden behind others, saving on memory bandwidth for unnecessary texture lookups.[2]
There are two main disadvantages of the tiled approach. One is that some triangles may be drawn several times if they overlap several tiles. This means the total rendering time would be higher than an immediate-mode rendering system. There are also possible issues when the tiles have to be stitched together to make a complete image, but this problem was solved long ago[citation needed]. More difficult to solve is that some image techniques are applied to the frame as a whole, and these are difficult to implement in a tiled render where the idea is to not have to work with the entire frame. These tradeoffs are well known, and of minor consequence for systems where the advantages are useful; tiled rendering systems are widely found in handheld computing devices.
Tiled rendering should not be confused with tiled/nonlinearframebuffer addressing schemes, which make adjacent pixels also adjacent in memory.[3] These addressing schemes are used by a wide variety of architectures, not just tiled renderers.
Much of the early work on tiled rendering was done as part of the Pixel Planes 5 architecture (1989).[4][5]
The Pixel Planes 5 project validated the tiled approach and invented a lot of the techniques now viewed as standard for tiled renderers. It is the work most widely cited by other papers in the field.
The tiled approach was also known early in the history of software rendering. Implementations ofReyes rendering often divide the image into "tile buckets".
Early in the development of desktop GPUs, several companies developed tiled architectures. Over time, these were largely supplanted by immediate-mode GPUs with fast custom external memory systems.
Major examples of this are:
Examples of non-tiled architectures that use large on-chip buffers are:
Due to the relatively low external memory bandwidth, and the modest amount of on-chip memory required, tiled rendering is a popular technology for embedded GPUs. Current examples include:
Tile-based immediate mode rendering (TBIM):
Tile-based deferred rendering (TBDR):
Vivante produces mobile GPUs which have tightly coupled frame buffer memory (similar to the Xbox 360 GPU described above). Although this can be used to render parts of the screen, the large size of the rendered regions means that they are not usually described as using a tile-based architecture.