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| Designer | Xilinx |
|---|---|
| Bits | 32-bit/64-bit (32 → 64) |
| Version | 11.0 |
| Design | RISC |
| Encoding | Fixed |
| Endianness | Little (Big) |
| Open | No |
| Registers | |
| 32 × 32 bits | |
TheMicroBlaze is asoft microprocessor core designed forXilinxfield-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.
MicroBlaze was introduced in 2002.[1]
In terms of its instruction set architecture, MicroBlaze is similar to theRISC-basedDLX architecture described in a popular computer architecture book byPatterson andHennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances.
The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, theAXI interconnect, is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used theCoreConnect PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly (or through an AXI interconnect). For access to local-memory (FPGARAM), MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage. User-defined coprocessors are supported through dedicated AXI4-Stream connections. The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.
Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage, 5-stage, or 8-stage), embedded peripherals,memory management unit, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area. The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of more than 700MHz (on Virtex UltraScale+FPGA family). Also, keyprocessor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed (e.g. multiply, divide, and floating point operations). This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements.
With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as theLinux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory model, e.g.FreeRTOS or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hard CPU core (such as theARM Cortex-A9 in theZynq).
MicroBlaze V is based on theRISC-V architecture.
Fast Simplex Link (FSL) is a 32-bit wide interface onMicroBlaze. The FSL channels are uni-directional, point-to-pointdata streaming interfaces.[2] A MicroBlaze processor supports up to eight FSL channels.[3] This interface allows MicroBlaze processors to communicate with peripherals or other processors.[4] The FSL can be used for extending the processor execution unit with customhardware accelerators thanks to a low latency dedicatedinterface to the processor pipeline. In addition, the same FSL channel can be used to transmit or receive either control or data words. The interface isFIFO, and a separate bit indicates whether the transmitted, or received, word is control or data information.[5] FSL has low latency compared toCoreConnect's On-chip Peripheral Bus.[6]
Xilinx'sVivado Design Suite is the development environment for building current MicroBlaze (orARM - see Zynq) embedded processor systems in Xilinx FPGAs. Older versions used Xilinx's EDK (Embedded Development Kit) development package.
Designers use the Vivado IP Integrator to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.) The IP Integrator converts the designer's block design into a synthesizeableRTL description (Verilog orVHDL), and automates the implementation of the embedded system (from RTL to the bitstream-file.) For the MicroBlaze core, Vivado generates an encrypted (non human-readable) netlist.
The SDK handles the software that will execute on the embedded system. Powered by theGNU toolchain (GNU Compiler Collection,GNU Debugger), the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system. Xilinx's tools provides the possibility of running software in simulation, or using a suitable FPGA-board to download and execute on the actual system.
Purchasers of Vivado are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties. The license does not grant the right to use MicroBlaze outside of Xilinx's devices.
Alternative compilers and development tools have been made available fromAltium but an EDK installation and license is still required.
In June 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux kernel source tree. This work was performed by Michal Simek and supported by PetaLogix and Xilinx.
In 2009, MicroBlaze GNU tools support was contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6[7]
Support was added toLLVM in April 2010,[8] but subsequently removed in July 2013[9] due to a lack of maintainer.
Support has been added for the Xilinx MicroBlaze softcore processor (microblaze-elf) embedded target.