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| Bits | 32-bit |
|---|---|
| Introduced | 1987; 39 years ago (1987) |
| Design | RISC |
| Predecessor | Stanford MIPS |
MIPS-X is areduced instruction set computer (RISC)microprocessor andinstruction set architecture (ISA) developed as a follow-on project to theMIPS project atStanford University by the same team that developed MIPS. The project was supported by the Defense Advanced Research Projects Agency (DARPA) and began in 1984. Its final form was described in a set of papers released in 1986–87. Unlike its older cousin, MIPS-X was never commercialized as aworkstationcentral processing unit (CPU), and has mainly been seen inembedded system designs based on chips designed byIntegrated Information Technology (IIT) for use indigital video applications.
MIPS-X, while designed by the same team and architecturally very similar, is instruction-set incompatible with the mainlineMIPS architecture R-series processors. The MIPS-X processor introduced the concept of a delayed branch, which includes twodelay slots.[1] An MIPS-X processor also includes a Processor Status Word (PSW) register. The PSW register contains some flags that enableinterruptions, overflow exceptions and other status information.[2] The MIPS-X processor is obscure enough that, as of November 20, 2005, support for it is provided only by specialist developers (such asGreen Hills Software), and is notably missing from theGNU Compiler Collection (GCC).
MIPS-X has become important amongDVD playerfirmwarehackers, since manyDVD players (especially low-end devices) use chips based on the IIT design (and produced byESS Technology), as their central processor. Devices such as the ESS VideoDrivesystem on a chip (SoC) also include adigital signal processor (DSP) (coprocessor) for decoding MPEG audio and video streams.
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