Western Digital MCP-1600

MCP-1600 microprocessor with WD16 microcode in five 40-pin packages.
General information
Launched	1975; 51 years ago (1975)
Common manufacturer	Western Digital
Performance
Max.CPUclock rate	to 3.3 MHz
Data width	8 (microdata), 18 (microcode), 16 (macrodata)
Address width	11 (microcode), 16 (macrodata)
Physical specifications
Package	4 or 5 x 40-pinDIP
Architecture and classification
Number of instructions	98
History
Successor	none

TheMCP-1600 is a multi-chip16-bitmicroprocessor introduced byWestern Digital in 1975 and produced through the early 1980s.^[2][3] Used in thePascal MicroEngine, theWD16 processor in theAlpha Microsystems AM-100, and theDECLSI-11 microcomputer,^[4] a cost-reduced and compact implementation of the DECPDP-11.

There are three types of chips in the chip-set:

• CP1611 RALU - RegisterALU chip
• CP1621 CON - Control chip
• CP1631 MICROM - Mask-programmedmicrocodeROM chip (512 – 22 bit words)

The chips use a 3.3MHzfour phase clock and three power supply voltages (+5V, +12V, and -5V), as required by theN-channelsilicon gate process then available at Western Digital. Internally the MCP-1600 is a (relatively fast) 8-bit processor that can be micro-programmed to emulate a 16-bit CPU. All byte operations execute in one clock period; word operations and branches take two clocks. Up to four MICROMs are supported, but usually two or three could hold the needed microprogram for a processor.^[5]

The register file consists of 26 8-bit registers. Ten may be addressed directly by the microinstruction (Rx), four may be addressed either directly or indirectly (Rx/Gx), and the remaining 12 may be addressed only indirectly (Gx). Indirect addressing is via a 3-bit G register which is usually loaded with the register field of the PDP-11 instruction.^[1]

The most significant feature of the MCP-1600 is its Programmable Translation Array (PTA). The PTA serves to generate new microinstruction fetch addresses as a function of several parameters. These parameters are those which are normally considered during the decode of a macroinstruction. The PTA was designed specifically to eliminate most of the overhead of macroinstruction translation. Essentially a macroinstruction opcode is quickly translated into an address that is loaded onto the Location Counter, creating a jump to the appropriate microcode to handle the macroinstruction.^[5]

John Wallace was the Project Manager and designed the 1621, Mike Briner designed the 1611, and later became a Senior VP atSilicon Storage Technology. Bill Pohlman was the design engineering manager and he later was Project Manager for theIntel 8086 processor.

Microcode could be developed using aDECLSI-11 computer with the KUV11-AAWritable Control Store (WCS) option. This option allowed programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set. The WCS is a quadQ-Bus board with a ribbon cable connecting to an open MCP-1600 microcode ROM socket.^[6]

In January 1976, the three-chip minimum MCP-1600 configuration was offered at $159 ($880 in 2024) in 100-999 quantities.^[7] In March 1976, it was announced thatNational Semiconductor would second-source the MCP-1600. It is unclear whether any were produced by National.^[8]

A clone of the CP1611 and CP1621 was manufactured in theSoviet Union under thedesignation KR581IK1 and KR581IK2 (Russian:КР581ИК1 and КР581ИК2).^[9] The Soviet 581 series included other members of the MCP-1600 family as well.^[10]

cp16sim is an open source MCP-1600 simulator. Written inC, it emulates the MCP-1600 processor and its PTA executing the code found on the WD9000 Pascal Microengine processor. As of 2016 it is unfinished. "It works well enough to execute the first few dozen p-code instructions of the ACD PDQ-3 boot ROM before going into the weeds." It is released under theGNU General Public License version 3.^[11]

• Die photos from LSI-11 chip set
• 
  CP1611 RALU chip
• 
  CP1621 Control chip
• 
  CP1631 MICROM chip

• 16-bit microprocessors
• Western Digital products

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