 Intergraph Clipper C4 (C400) CPU | |
| Designer | |
|---|---|
| Bits | 32-bit |
| Introduced | 1986; 40 years ago (1986) |
| Design | RISC-like |
TheClipper architecture is a32-bitreduced instruction set computer (RISC)-likecentral processing unit (CPU)instruction set architecture designed byFairchild Semiconductor. The architecture had little market success: the onlycomputer manufacturers to create major product lines using Clipper processors wereIntergraph andHigh Level Hardware, although Opus Systems offered a product based on the Clipper as part of its PersonalMainframe range.[1] The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.[2]
The Clipper architecture used a simplified instruction set compared to earliercomplex instruction set computer (CISC) architectures, but it did incorporate some more complex instructions than were present in other contemporary RISC processors. These instructions were implemented in a so-called Macro Instructionread-only memory (ROM) within the Clipper CPU. This scheme allowed the Clipper to have somewhat highercode density than other RISC CPUs.
The initial Clippermicroprocessor produced by Fairchild was the C100, which became available in 1986. This was followed by the faster C300 from Intergraph in 1988. The final model of the Clipper was the C400, released in 1990, which was extensively redesigned to be faster and added morefloating-point arithmetic registers. The C400 processor combined two key architectural techniques to achieve a new level of performance:superscalar instruction dispatch andsuperpipelined operation.
While many processors of the time used either superscalar instruction dispatch orsuperpipelined operation, the Clipper C400 was the first processor to use both.[3]
Intergraph started work on a subsequent Clipper processor design known as the C5, but this was never completed or released. Nonetheless, some advanced processor design techniques were devised for the C5, and Intergraph was grantedpatents on these. These patents, along with the original Clipper patents, have been the basis of patent-infringement lawsuits by Intergraph againstIntel and other companies.[4]
Unlike many other microprocessors, the Clipper processors were actually sets of several distinct chips. The C100 and C300 consist of three chips: one central processing unit containing both an integer unit and afloating point unit, and twocache andmemory management units (CAMMUs), one responsible for data and one for instructions. The CAMMUs contained caches,translation lookaside buffers, and support formemory protection andvirtual memory. The C400 consists of four basic units: an integer CPU, an FPU, an MMU, and a cache unit. The initial version used one chip each for the CPU and FPU and discrete elements for the MMU and cache unit, but in later versions the MMU and cache unit were combined into one CAMMU chip.
The Clipper has 16 integer registers (R15 is used as the stack pointer), 16 floating-point registers (limited to 8 in early implementations), plus a program counter (PC), a processor status word (PSW) containing ALU and FPU status flags and trap enables, and a system status word (SSW) containing external interrupt enable, user/supervisor mode, and address translation control bits.
User and supervisor modes has separate banks of integer registers. Interrupt handling consisted of saving the PC, PSW, and SSW on the stack, clearing the PSW, and loading the PC and SSW from a memory trap vector.
The Clipper is aload/store architecture, where arithmetic operations could only specify register or immediate operands. The basic instruction "parcel" is 16 bits: 8 bits of opcode, 4 bits of source register, and 4 bits of destination register. Immediate-operand forms allow 1 or 2 following instruction parcels to specify a 16-bit (sign-extended) or 32-bit immediate operand. The processor is uniformly little-endian, including immediate operands.
A special "quick" encoding with a 4-bit unsigned operand is provided for add, subtract, load (move quick to register), and not (move complement of quick to register).
Addressing modes for load/store and branch instructions are as follows. All displacements are sign-extended.
In addition to the usual logical and arithmetic operations, the processor supports:
More complex macro instructions allow:
Most instructions allow an arbitrary stack pointer register to be specified, but except for the user register save/restore, the multiple-register operations can use only R15.
Intergraph sold several generations of Clipper systems, including bothservers andworkstations. These systems included the InterAct, InterServe, and InterPro product lines and were targeted largely at thecomputer-aided design (CAD) market.
Fairchild promoted the CLIX operating system, a version ofUNIX System V, for use with the Clipper. Intergraph adopted CLIX for its Clipper-based systems and continued to develop it; this was the only operating system available for those systems. Intergraph did work on a version ofMicrosoftWindows NT for Clipper systems and publicly demonstrated it, but this effort was canceled before release.[5] Intergraph decided to discontinue the Clipper line and instead began sellingx86 systems withWindows NT.
