Broadway

IBM Broadway microprocessor from the inside of aWii. The reference to Canada in the picture is related to where it was packaged i.e. by IBM Canada inBromont.
General information
Launched	2006
Discontinued	October 22nd, 2013
Designed by	IBM andNintendo
Common manufacturer	IBM Microelectronics
Performance
Max.CPUclock rate	729 MHz
Physical specifications
Cores	1
GPU	Hollywood
Cache
L1cache	32/32 kB
L2 cache	256 kB
Architecture and classification
Application	Wii
Technology node	90 nm (2006–2007), 65 nm (2007–2013)
Microarchitecture	PowerPC G3
Instruction set	PowerPC (PowerPC ISA 1.10)
Products, models, variants
Variant	PowerPC 750CL
History
Predecessor	Gekko
Successor	Espresso

Broadway is the codename of the32-bitcentral processing unit (CPU) used inNintendo'sWii home video game console. It was designed byIBM, and was initially produced using a90 nmSOI process and later produced with a65 nmSOI process.

According to IBM, the processor consumes 20% less power than its predecessor, the 180 nmGekko used in theGameCubevideo game console.^[1]

Broadway was produced by IBM at their semiconductor development and manufacturing facility inEast Fishkill,New York (now owned byGlobalFoundries). The bond, assembly, and test operation for the Broadway module was performed at the IBM facility inBromont,Quebec. Very few official details have been released to the public by Nintendo or IBM; unofficial reports claim it is derived from the 486MHzGekko architecture used in the GameCube and runs 50% faster at 729 MHz.^[2]

ThePowerPC 750CL, released in 2006, is a stock CPU offered by IBM; it is virtually identical to Broadway, but was provided in multiple clock speed variants (ranging from 400 MHz–1000 MHz.)^[3][4][5]

• 90 nanometer process technology,shrunk to 65 nm in 2007.^[6]
• SuperscalarOut-of-order executionPowerPC core, specially modified for the Wii platform
• IBMsilicon on insulator (SOI) technology
• Backward compatible with theGekko processor
• 729 MHz
• 4 stages long Two integerALUs (IU1 and IU2) – 32 bit
• 7 stages long 64-bit floating-point unit (FPU) (or 2 × 32-bit SIMD, often found under the denomination "paired singles")
• Branch Prediction Unit (BPU)
• Load-Store Unit (LSU)
• System Register Unit (SRU)
• Memory Management Unit (MMU)
• Branch Target Instruction Cache (BTIC)
• SIMD Instructions – PowerPC750 + Roughly 50 newSIMD instructions, geared toward3D graphics
• 64 kB L1 cache (32 kB instruction + 32 kB data)
• 256 kB L2 cache
• 2.9 GFLOPS

• 64-bit
• 243 MHz
• 1.944gigabytes per second bandwidth

Broadway
39X6735, 2006
90 nm, 21×21 mm package

Broadway A
43E4048, 2006-2007
90 nm, 21×21 mm package

Broadway B
43E5070, 2007-2008
65 nm, 21×21 mm package

Broadway-1
48J2662, 2008-2016
65 nm, 15×15 mm package

These images are illustrations and only approximately to scale.

• Nintendo chips
• Wii hardware
• IBM microprocessors
• PowerPC microprocessors

• Articles with short description
• Short description is different from Wikidata